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android_device_tecno_LG8n/configs/nfc/libnfc-nxp_RF.conf
dodyirawan85 0de96303d2 X6833B: Configure NFC stack 
Signed-off-by: dodyirawan85 <40514988+dodyirawan85@users.noreply.github.com>
2023-12-26 09:13:08 +07:00

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################################################################################
# NXP RF Eval1_SLALM_CFG2_EFM_40x20 configuration settings for FW Version = 12.01.16
#
# A0, 35, 01, 00, RF_CLIF_CFG_BOOT
# A0, 0D, 03, 00, 43, A0, RF_CLIF_CFG_BOOT CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 04, 00, 42, FF, FF, RF_CLIF_CFG_BOOT CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 04, 44, 00, 08, F6, 00, RF_CLIF_CFG_IDLE CLIF_ANA_RX_REG
# A0, 0D, 06, 04, 45, 80, 40, 00, 00, RF_CLIF_CFG_IDLE CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 04, 4A, 00, 00, 00, 00, RF_CLIF_CFG_IDLE CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 04, 47, 00, RF_CLIF_CFG_IDLE CLIF_ANA_AGC_REG
# A0, 0D, 06, 04, 35, 00, 3E, 00, 00, RF_CLIF_CFG_IDLE CLIF_AGC_INPUT_REG
# A0, 0D, 06, 04, 33, 0F, 40, 04, 00, RF_CLIF_CFG_IDLE CLIF_AGC_CONFIG0_REG
# A0, 0D, 03, 04, 40, 00, RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG
# A0, 0D, 06, 06, 35, F4, 05, 70, 02, RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
# A0, 0D, 06, 06, 42, F8, 40, FF, FF, RF_CLIF_CFG_INITIATOR CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, C2, 35, 00, 3E, 00, 03, RF_CLIF_EXT_FIELD_ON CLIF_AGC_INPUT_REG
# A0, 0D, 06, C2, 34, F7, 7F, 10, 08, RF_CLIF_EXT_FIELD_ON CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, C2, 33, 03, 40, 04, 80, RF_CLIF_EXT_FIELD_ON CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 08, 2D, 0D, 25, 2C, 01, RF_CLIF_CFG_TARGET CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 08, 44, 04, 04, C4, 00, RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
# A0, 0D, 06, 08, 30, 70, 00, 18, 00, RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 08, 45, 83, 60, 40, 05, RF_CLIF_CFG_TARGET CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 08, 42, 00, 02, FF, FF, RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 08, 16, AE, 00, 1F, 00, RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 08, 15, 00, RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 08, 37, 08, 76, 00, 00, RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 06, 09, 30, 00, 00, 00, 00, RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 09, 37, 00, 00, 00, 00, RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 06, 09, 42, 01, 10, FF, FF, RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 72, 03, 3D, RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 04, 72, 42, F8, 40, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 72, 16, 01, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 72, 15, 01, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 72, 4A, 53, 07, 00, 1B, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 72, 0D, 24, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 72, 14, 24, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 3C, 2D, DC, 40, 04, 00, RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3C, 44, 66, 0A, 00, 00, RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 06, 74, 4A, 56, 07, 01, 1B, RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 04, 74, 42, 68, 40, RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 74, 16, 00, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 74, 15, 00, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 74, 0D, 11, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 74, 14, 11, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 3E, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3E, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 76, 4A, 56, 07, 01, 1B, RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 04, 76, 42, 68, 40, RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 76, 16, 00, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 76, 15, 00, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 76, 0D, 08, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 76, 14, 08, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 40, 2D, 05, 45, 1E, 01, RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 40, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 04, 78, 42, F0, 40, RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 78, 4A, 11, 07, 01, 1B, RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 78, 16, 00, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 78, 15, 00, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 78, 0D, 04, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 78, 14, 04, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 4C, 44, 65, 0A, 00, 00, RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4C, 2D, 15, 34, 1F, 01, RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 82, 4A, 33, 07, 00, 07, RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 04, 82, 42, 68, 40, RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 82, 0F, 6C, 01, 04, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_SYMBOL_CONFIG_REG
# A0, 0D, 03, 82, 16, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 82, 15, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 4E, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4E, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 84, 4A, 13, 07, 01, 07, RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 04, 84, 42, 68, 40, RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 84, 16, 00, RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 84, 15, 00, RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 50, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 50, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 86, 4A, 12, 07, 01, 07, RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 04, 86, 42, 68, 40, RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 86, 16, 00, RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 86, 15, 00, RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 5E, 2D, 0D, 48, 0C, 01, RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 5E, 44, 55, 08, 00, 00, RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 60, 2D, 0D, 5A, 0C, 01, RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 60, 44, 55, 08, 00, 00, RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 04, 94, 42, 78, 40, RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 94, 4A, 43, 07, 00, 07, RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 94, 16, 00, RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 94, 15, 00, RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 96, 42, 80, 40, RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 96, 4A, 11, 07, 01, 07, RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 96, 16, 00, RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 96, 15, 00, RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 1C, 44, 05, 04, C4, 00, RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 03, 24, 03, 7F, RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 06, 70, 16, 8E, 00, 1F, 00, RF_CLIF_CFG_BR_848_T_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 28, 16, 00, RF_CLIF_CFG_TECHNO_T_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 2C, 16, 00, RF_CLIF_CFG_TECHNO_T_TXF_P CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 06, 34, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 36, 30, E0, 00, 30, 00, RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 36, 45, 70, RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 03, 37, 45, 60, RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 38, 30, 40, 00, 20, 00, RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 38, 44, 02, 04, C4, 00, RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 3A, 30, 26, 00, 08, 00, RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 3A, 44, 11, 00, C4, 00, RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 44, 30, 70, 00, 18, 00, RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 44, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 46, 30, B0, 00, 45, 00, RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 48, 30, B0, 00, 45, 00, RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 4A, 30, 70, 00, 18, 00, RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 56, 30, 00, RF_CLIF_CFG_BR_212_T_RXF CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 0C, 45, C3, 82, 71, 05, RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 03, 10, 44, 60, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
# A0, 0D, 06, 10, 30, 70, 00, 18, 00, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 10, 48, 10, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 06, 10, 45, 80, 40, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 10, 2D, 0D, 25, 2C, 01, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 03, 10, 35, 0C, RF_CLIF_CFG_I_ACTIVE CLIF_AGC_INPUT_REG
# A0, 0D, 06, 11, 30, 00, 00, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 11, 48, 00, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 06, 11, 85, 00, 00, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_BBA_CONTROL_REG
# A0, 0D, 06, 22, 44, 05, 04, C4, 00, RF_CLIF_CFG_TECHNO_I_RXF_A CLIF_ANA_RX_REG
# A0, 0D, 06, 62, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_I_RXA_A CLIF_ANA_RX_REG
# A0, 0D, 03, 12, 16, 00, RF_CLIF_CFG_T_ACTIVE CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 06, 12, 37, 00, 00, 00, 00, RF_CLIF_CFG_T_ACTIVE CLIF_TX_CONTROL_REG
# A0, 0D, 03, 12, 35, 0C, RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG
# A0, 0D, 06, CC, 42, F8, 40, FF, FF, RF_CLIF_WL_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, CC, 4A, 53, 07, 00, 1B, RF_CLIF_WL_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, CE, 42, 78, 40, FF, FF, RF_CLIF_WL_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, CE, 4A, 43, 07, 00, 07, RF_CLIF_WL_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, D0, 42, 80, 40, FF, FF, RF_CLIF_WL_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, D0, 4A, 11, 07, 01, 07, RF_CLIF_WL_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 98, 16, 01, RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 98, 15, 01, RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 9A, 16, 00, RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 9A, 15, 00, RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 9C, 16, 00, RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 9C, 15, 00, RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, CA, 42, 68, 40, RF_CLIF_CFG_STAG CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, CA, 44, 65, 0A, 00, 00, RF_CLIF_CFG_STAG CLIF_ANA_RX_REG
# A0, 0D, 06, CA, 2D, 15, 34, 1F, 01, RF_CLIF_CFG_STAG CLIF_SIGPRO_RM_CONFIG1_REG
#
# *** Eval1_SLALM_CFG2_EFM_40x20 FW VERSION = 12.01.16 ***
NXP_RF_CONF_BLK_1={
20, 02, FA, 1F,
A0, 35, 01, 00,
A0, 0D, 03, 00, 43, A0,
A0, 0D, 04, 00, 42, FF, FF,
A0, 0D, 06, 04, 44, 00, 08, F6, 00,
A0, 0D, 06, 04, 45, 80, 40, 00, 00,
A0, 0D, 06, 04, 4A, 00, 00, 00, 00,
A0, 0D, 03, 04, 47, 00,
A0, 0D, 06, 04, 35, 00, 3E, 00, 00,
A0, 0D, 06, 04, 33, 0F, 40, 04, 00,
A0, 0D, 03, 04, 40, 00,
A0, 0D, 06, 06, 35, F4, 05, 70, 02,
A0, 0D, 06, 06, 42, F8, 40, FF, FF,
A0, 0D, 06, C2, 35, 00, 3E, 00, 03,
A0, 0D, 06, C2, 34, F7, 7F, 10, 08,
A0, 0D, 06, C2, 33, 03, 40, 04, 80,
A0, 0D, 06, 08, 2D, 0D, 25, 2C, 01,
A0, 0D, 06, 08, 44, 04, 04, C4, 00,
A0, 0D, 06, 08, 30, 70, 00, 18, 00,
A0, 0D, 06, 08, 45, 83, 60, 40, 05,
A0, 0D, 06, 08, 42, 00, 01, FF, FF,
A0, 0D, 06, 08, 16, AE, 00, 1F, 00,
A0, 0D, 03, 08, 15, 00,
A0, 0D, 06, 08, 37, 48, 76, 00, 00,
A0, 0D, 06, 09, 30, 00, 00, 00, 00,
A0, 0D, 06, 09, 37, 00, 00, 00, 00,
A0, 0D, 06, 09, 42, 01, 10, FF, FF,
A0, 0D, 03, 72, 03, 3D,
A0, 0D, 04, 72, 42, F8, 40,
A0, 0D, 03, 72, 16, 01,
A0, 0D, 03, 72, 15, 01,
A0, 0D, 06, 72, 4A, 53, 07, 00, 1B
}
NXP_RF_CONF_BLK_2={
20, 02, FB, 22,
A0, 0D, 03, 72, 0D, 24,
A0, 0D, 03, 72, 14, 24,
A0, 0D, 06, 3C, 2D, DC, 30, 04, 00,
A0, 0D, 06, 3C, 44, 77, 0A, 00, 00,
A0, 0D, 06, 74, 4A, 56, 07, 01, 1B,
A0, 0D, 04, 74, 42, 68, 40,
A0, 0D, 03, 74, 16, 00,
A0, 0D, 03, 74, 15, 00,
A0, 0D, 03, 74, 0D, 11,
A0, 0D, 03, 74, 14, 11,
A0, 0D, 06, 3E, 2D, 05, 35, 1E, 01,
A0, 0D, 06, 3E, 44, 65, 09, 00, 00,
A0, 0D, 06, 76, 4A, 56, 07, 01, 1B,
A0, 0D, 04, 76, 42, 68, 40,
A0, 0D, 03, 76, 16, 00,
A0, 0D, 03, 76, 15, 00,
A0, 0D, 03, 76, 0D, 08,
A0, 0D, 03, 76, 14, 08,
A0, 0D, 06, 40, 2D, 05, 45, 1E, 01,
A0, 0D, 06, 40, 44, 65, 09, 00, 00,
A0, 0D, 04, 78, 42, F0, 40,
A0, 0D, 06, 78, 4A, 11, 07, 01, 1B,
A0, 0D, 03, 78, 16, 00,
A0, 0D, 03, 78, 15, 00,
A0, 0D, 03, 78, 0D, 04,
A0, 0D, 03, 78, 14, 04,
A0, 0D, 06, 4C, 44, 77, 0A, 00, 00,
A0, 0D, 06, 4C, 2D, 15, 34, 1F, 01,
A0, 0D, 06, 82, 4A, 33, 07, 00, 07,
A0, 0D, 04, 82, 42, 68, 40,
A0, 0D, 06, 82, 0F, 6C, 01, 04, 00,
A0, 0D, 03, 82, 16, 00,
A0, 0D, 03, 82, 15, 00,
A0, 0D, 06, 4E, 44, 65, 09, 00, 00
}
NXP_RF_CONF_BLK_3={
20, 02, FB, 21,
A0, 0D, 06, 4E, 2D, 05, 35, 1E, 01,
A0, 0D, 06, 84, 4A, 13, 07, 01, 07,
A0, 0D, 04, 84, 42, 68, 40,
A0, 0D, 03, 84, 16, 00,
A0, 0D, 03, 84, 15, 00,
A0, 0D, 06, 50, 44, 65, 09, 00, 00,
A0, 0D, 06, 50, 2D, 05, 35, 1E, 01,
A0, 0D, 06, 86, 4A, 12, 07, 01, 07,
A0, 0D, 04, 86, 42, 68, 40,
A0, 0D, 03, 86, 16, 00,
A0, 0D, 03, 86, 15, 00,
A0, 0D, 06, 5E, 2D, 0D, 48, 0C, 01,
A0, 0D, 06, 5E, 44, 55, 08, 00, 00,
A0, 0D, 06, 60, 2D, 0D, 5A, 0C, 01,
A0, 0D, 06, 60, 44, 55, 08, 00, 00,
A0, 0D, 04, 94, 42, 78, 40,
A0, 0D, 06, 94, 4A, 43, 07, 00, 07,
A0, 0D, 03, 94, 16, 00,
A0, 0D, 03, 94, 15, 00,
A0, 0D, 04, 96, 42, 80, 40,
A0, 0D, 06, 96, 4A, 11, 07, 01, 07,
A0, 0D, 03, 96, 16, 00,
A0, 0D, 03, 96, 15, 00,
A0, 0D, 06, 1C, 44, 05, 04, C4, 00,
A0, 0D, 03, 24, 03, 7D,
A0, 0D, 06, 70, 16, 8E, 00, 1F, 00,
A0, 0D, 03, 28, 16, 00,
A0, 0D, 03, 2C, 16, 00,
A0, 0D, 06, 34, 44, 77, 04, C4, 00,
A0, 0D, 06, 36, 30, E0, 00, 30, 00,
A0, 0D, 03, 36, 45, 70,
A0, 0D, 03, 37, 45, 60,
A0, 0D, 06, 38, 30, 40, 00, 20, 00
}
NXP_RF_CONF_BLK_4={
20, 02, FA, 1E,
A0, 0D, 06, 38, 44, 02, 04, C4, 00,
A0, 0D, 06, 3A, 30, 26, 00, 08, 00,
A0, 0D, 06, 3A, 44, 11, 00, C4, 00,
A0, 0D, 06, 44, 30, 70, 00, 18, 00,
A0, 0D, 06, 44, 44, 04, 04, C4, 00,
A0, 0D, 06, 46, 30, B0, 00, 45, 00,
A0, 0D, 06, 48, 30, B0, 00, 45, 00,
A0, 0D, 06, 4A, 30, 70, 00, 18, 00,
A0, 0D, 03, 56, 30, 00,
A0, 0D, 06, 0C, 45, C3, 82, 71, 05,
A0, 0D, 03, 10, 44, 60,
A0, 0D, 06, 10, 30, 70, 00, 18, 00,
A0, 0D, 03, 10, 48, 10,
A0, 0D, 06, 10, 45, 80, 40, 00, 00,
A0, 0D, 06, 10, 2D, 0D, 25, 2C, 01,
A0, 0D, 03, 10, 35, 0C,
A0, 0D, 06, 11, 30, 00, 00, 00, 00,
A0, 0D, 03, 11, 48, 00,
A0, 0D, 06, 11, 85, 00, 00, 00, 00,
A0, 0D, 06, 22, 44, 05, 04, C4, 00,
A0, 0D, 06, 62, 44, 04, 04, C4, 00,
A0, 0D, 03, 12, 16, 00,
A0, 0D, 06, 12, 37, 00, 00, 00, 00,
A0, 0D, 03, 12, 35, 0C,
A0, 0D, 06, CC, 42, F8, 40, FF, FF,
A0, 0D, 06, CC, 4A, 53, 07, 00, 1B,
A0, 0D, 06, CE, 42, 78, 40, FF, FF,
A0, 0D, 06, CE, 4A, 43, 07, 00, 07,
A0, 0D, 06, D0, 42, 80, 40, FF, FF,
A0, 0D, 06, D0, 4A, 11, 07, 01, 07
}
NXP_RF_CONF_BLK_5={
20, 02, A7, 0B,
A0, 0D, 03, 98, 16, 01,
A0, 0D, 03, 98, 15, 01,
A0, 0D, 03, 9A, 16, 00,
A0, 0D, 03, 9A, 15, 00,
A0, 0D, 03, 9C, 16, 00,
A0, 0D, 03, 9C, 15, 00,
A0, 0D, 04, CA, 42, 68, 40,
A0, 0D, 06, CA, 44, 65, 0A, 00, 00,
A0, 0D, 06, CA, 2D, 15, 34, 1F, 01,
A0, 0B, 57, 11, 11, 90, 5A, 0F, 4E, 00, 47, 15, B7, AA, 47, 9F, A7, 99, 5C, 9F, 97, 99, 67, 9F, 97, 99, 69, 9F, 97, 00, 73, 9F, 07, 00, 75, 9F, 07, 00, 80, 9F, 07, 00, 84, 9F, 07, 00, 8D, 9F, 07, 00, 8F, 9F, 07, 00, 99, 9F, 04, 00, 9B, 9F, 04, 00, A6, 9F, 04, 00, A8, 9F, 04, 00, B2, 9F, 02, 00, BB, 9F, 00, 00, C1, 9F, 00, 00, CC, 1F, 00, 00, D6, 1F, 00, 00,
A0, AF, 0C, 03, C0, 80, A0, 00, 03, 80, 80, A0, 00, 77, 08
}
###############################################################################
# Core configuration extensions
# It includes
# Wired mode settings A0ED, A0EE
# Tag Detector A040, A041, A043
# Low Power mode A007
# Clock settings A002, A003
# PbF settings A008
# Clock timeout settings A004
# UICC SWP_INT1_EN_CFG - A0, EC
# UICC2 SWP_INT2_EN_CFG - A0, ED,
# eSE (SVDD) PWR REQ settings A0F2
# Window size A0D8
# DWP Speed A0D5
# How eSE connected to PN553 A012
# UICC2 bit rate A0D1
# SWP1A interface A0D4
# DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
# For Symmetric baud rate UICC's set A086 to 77
# A06B0101 to enable the Mifare Classic fix.
NXP_CORE_CONF_EXTN={20, 02, 85, 15,
A0, EC, 01, 01,
A0, ED, 01, 00,
A0, 5E, 01, 01,
A0, 12, 01, 02,
A0, 40, 01, 01,
A0, 41, 01, 06,
A0, 42, 01, 0F,
A0, 43, 01, 04,
A0, 46, 02, BA, 27,
A0, 47, 02, BA, 27,
A0, DD, 01, 2D,
A0, D1, 01, 06,
A0, D4, 01, 00,
A0, 37, 01, 35,
A0, 86, 01, 77,
A0, 38, 04, 01, 01, 00, 00,
A0, 3A, 08, E1, 00, E1, 00, E1, 00, E1, 00,
A0, 29, 17, 1D, 07, 00, 1D, 00, 02, 00, 1D, 00, 02, 00, 40, F3, F3, 00, 43, F3, F3, 38, 70, 00, 00, 00,
A0, 03, 01, 03,
A0, 20, 08, 08, 52, A2, 82, 30, 01, E1, 02,
A0, 26, 08, 20, 41, A3, 01, 88, 01, E2, 02
}
# for PN80T backup
#NXP_CORE_CONF_EXTN={20, 02, 8B, 19,
# A0, EC, 01, 01,
# A0, ED, 01, 00,
# A0, 5E, 01, 01,
# A0, 12, 01, 02,
# A0, 40, 01, 01,
# A0, 41, 01, 05,
# A0, 42, 01, 0F,
# A0, 43, 01, 04,
# A0, 46, 02, BA, 27,
# A0, 47, 02, BA, 27,
# A0, D1, 01, 06,
# A0, D4, 01, 00,
# A0, 37, 01, 35,
# A0, D8, 01, 02,
# A0, D5, 01, 0A,
# A0, B2, 01, 1E,
# A0, DD, 01, 2D,
# A0, F2, 01, 01,
# A0, 9F, 02, 08, 08,
# A0, 86, 01, 77,
# A0, 6B, 01, 01,
# A0, 85, 04, 50, 0A, 28, 3C,
# A0, 38, 04, 08, 08, 08, 00,
# A0, 3A, 08, AA, 00, AA, 00, AA, 00, AA, 00,
# A0, 29, 17, 1B, 07, 00, 1D, 00, 02, 00, 1D, 00, 02, 00, 40, F3, F3, 00, 43, F3, F3, 38, 70, 00, 00, 00
# }
###############################################################################
# Core configuration settings
# It includes
# 18 - Poll Mode NFC-F: PF_BIT_RATE
# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
# 33 - Lis. Mode NFC-A: LA_NFCID1
# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
# 58 - Lis. Mode NFC-A: LI_A_RATS_TB1
# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
# 60 - Lis. Mode NFC-DEP: LN_WT
# 80 - Other Param.: RF_FIELD_INFO
# 81 - Other Param.: RF_NFCEE_ACTION
# 82 - Other Param.: NFCDEP_OP
# Add 58, 01, 74, for changing FWI while route IsoDep type-A to HCE:
# Fix bug AlmId 26307, Jingdong pay is failure on Lakala T1 POS.
# Default TB1 of HCE is 0x44. Change TB1 to 0x74,
# then change FWT from 4.8ms to 38.7ms.
# TB1: high nibble 4bits is FWI, low nibble 4bits is SFGI.
NXP_CORE_CONF={ 20, 02, 33, 11,
18, 01, 01,
21, 01, 00,
28, 01, 00,
30, 01, 04,
31, 01, 00,
32, 01, 20,
33, 00,
38, 01, 01,
50, 01, 02,
54, 01, 06,
58, 01, 74,
5B, 01, 00,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
68, 01, 01,
85, 01, 01
}
###############################################################################
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