485 lines
14 KiB
Plaintext
485 lines
14 KiB
Plaintext
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* Samsung Exynos5433 CMU (Clock Management Units)
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The Exynos5433 clock controller generates and supplies clock to various
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controllers within the Exynos5433 SoC.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
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which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
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domains and bus clocks.
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- "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
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which generates clocks for LLI (Low Latency Interface) IP.
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- "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
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which generates clocks for DRAM Memory Controller domain.
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- "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
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which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
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- "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
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which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
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- "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
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which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
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- "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
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which generates clocks for G2D/MDMA IPs.
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- "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
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which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
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- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
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which generates clocks for Cortex-A5/BUS/AUDIO clocks.
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- "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
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and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
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which generates global data buses clock and global peripheral buses clock.
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- "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
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which generates clocks for 3D Graphics Engine IP.
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- "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
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which generates clocks for GSCALER IPs.
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- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
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which generates clocks for Cortex-A53 Quad-core processor.
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- "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
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which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
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L2 cache controller.
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- "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
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which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
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- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
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which generates clocks for MFC(Multi-Format Codec) IP.
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- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
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which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
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- "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
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which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
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- "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
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which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
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IPs.
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- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
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which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- clocks: list of the clock controller input clock identifiers,
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from common clock bindings. Please refer the next section
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to find the input clocks for a given controller.
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- clock-names: list of the clock controller input clock names,
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as described in clock-bindings.txt.
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Input clocks for top clock controller:
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- oscclk
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- sclk_mphy_pll
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- sclk_mfc_pll
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- sclk_bus_pll
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Input clocks for cpif clock controller:
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- oscclk
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Input clocks for mif clock controller:
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- oscclk
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- sclk_mphy_pll
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Input clocks for fsys clock controller:
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- oscclk
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- sclk_ufs_mphy
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- aclk_fsys_200
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- sclk_pcie_100_fsys
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- sclk_ufsunipro_fsys
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- sclk_mmc2_fsys
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- sclk_mmc1_fsys
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- sclk_mmc0_fsys
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- sclk_usbhost30_fsys
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- sclk_usbdrd30_fsys
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Input clocks for g2d clock controller:
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- oscclk
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- aclk_g2d_266
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- aclk_g2d_400
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Input clocks for disp clock controller:
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- oscclk
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- sclk_dsim1_disp
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- sclk_dsim0_disp
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- sclk_dsd_disp
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- sclk_decon_tv_eclk_disp
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- sclk_decon_vclk_disp
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- sclk_decon_eclk_disp
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- sclk_decon_tv_vclk_disp
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- aclk_disp_333
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Input clocks for audio clock controller:
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- oscclk
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- fout_aud_pll
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Input clocks for bus0 clock controller:
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- aclk_bus0_400
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Input clocks for bus1 clock controller:
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- aclk_bus1_400
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Input clocks for bus2 clock controller:
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- oscclk
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- aclk_bus2_400
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Input clocks for g3d clock controller:
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- oscclk
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- aclk_g3d_400
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Input clocks for gscl clock controller:
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- oscclk
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- aclk_gscl_111
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- aclk_gscl_333
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Input clocks for apollo clock controller:
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- oscclk
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- sclk_bus_pll_apollo
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Input clocks for atlas clock controller:
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- oscclk
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- sclk_bus_pll_atlas
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Input clocks for mscl clock controller:
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- oscclk
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- sclk_jpeg_mscl
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- aclk_mscl_400
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Input clocks for mfc clock controller:
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- oscclk
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- aclk_mfc_400
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Input clocks for hevc clock controller:
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- oscclk
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- aclk_hevc_400
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Input clocks for isp clock controller:
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- oscclk
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- aclk_isp_dis_400
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- aclk_isp_400
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Input clocks for cam0 clock controller:
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- oscclk
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- aclk_cam0_333
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- aclk_cam0_400
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- aclk_cam0_552
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Input clocks for cam1 clock controller:
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- oscclk
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- sclk_isp_uart_cam1
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- sclk_isp_spi1_cam1
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- sclk_isp_spi0_cam1
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- aclk_cam1_333
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- aclk_cam1_400
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- aclk_cam1_552
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Optional properties:
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- power-domains: a phandle to respective power domain node as described by
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generic PM domain bindings (see power/power_domain.txt for more
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information).
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos5433.h header and can be used in device
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tree sources.
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Example 1: Examples of 'oscclk' source clock node are listed below.
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xxti: xxti {
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compatible = "fixed-clock";
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clock-output-names = "oscclk";
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#clock-cells = <0>;
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};
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Example 2: Examples of clock controller nodes are listed below.
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cmu_top: clock-controller@10030000 {
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compatible = "samsung,exynos5433-cmu-top";
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reg = <0x10030000 0x0c04>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"sclk_mphy_pll",
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"sclk_mfc_pll",
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"sclk_bus_pll";
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clocks = <&xxti>,
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<&cmu_cpif CLK_SCLK_MPHY_PLL>,
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<&cmu_mif CLK_SCLK_MFC_PLL>,
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<&cmu_mif CLK_SCLK_BUS_PLL>;
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};
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cmu_cpif: clock-controller@10fc0000 {
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compatible = "samsung,exynos5433-cmu-cpif";
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reg = <0x10fc0000 0x0c04>;
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#clock-cells = <1>;
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clock-names = "oscclk";
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clocks = <&xxti>;
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};
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cmu_mif: clock-controller@105b0000 {
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compatible = "samsung,exynos5433-cmu-mif";
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reg = <0x105b0000 0x100c>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"sclk_mphy_pll";
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clocks = <&xxti>,
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<&cmu_cpif CLK_SCLK_MPHY_PLL>;
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};
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cmu_peric: clock-controller@14c80000 {
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compatible = "samsung,exynos5433-cmu-peric";
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reg = <0x14c80000 0x0b08>;
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#clock-cells = <1>;
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};
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cmu_peris: clock-controller@10040000 {
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compatible = "samsung,exynos5433-cmu-peris";
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reg = <0x10040000 0x0b20>;
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#clock-cells = <1>;
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};
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cmu_fsys: clock-controller@156e0000 {
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compatible = "samsung,exynos5433-cmu-fsys";
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reg = <0x156e0000 0x0b04>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"sclk_ufs_mphy",
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"aclk_fsys_200",
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"sclk_pcie_100_fsys",
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"sclk_ufsunipro_fsys",
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"sclk_mmc2_fsys",
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"sclk_mmc1_fsys",
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"sclk_mmc0_fsys",
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"sclk_usbhost30_fsys",
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"sclk_usbdrd30_fsys";
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clocks = <&xxti>,
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<&cmu_cpif CLK_SCLK_UFS_MPHY>,
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<&cmu_top CLK_ACLK_FSYS_200>,
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<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
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<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
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<&cmu_top CLK_SCLK_MMC2_FSYS>,
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<&cmu_top CLK_SCLK_MMC1_FSYS>,
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<&cmu_top CLK_SCLK_MMC0_FSYS>,
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<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
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<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
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};
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cmu_g2d: clock-controller@12460000 {
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compatible = "samsung,exynos5433-cmu-g2d";
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reg = <0x12460000 0x0b08>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"aclk_g2d_266",
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"aclk_g2d_400";
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clocks = <&xxti>,
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<&cmu_top CLK_ACLK_G2D_266>,
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<&cmu_top CLK_ACLK_G2D_400>;
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power-domains = <&pd_g2d>;
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};
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cmu_disp: clock-controller@13b90000 {
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compatible = "samsung,exynos5433-cmu-disp";
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reg = <0x13b90000 0x0c04>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"sclk_dsim1_disp",
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"sclk_dsim0_disp",
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"sclk_dsd_disp",
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"sclk_decon_tv_eclk_disp",
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"sclk_decon_vclk_disp",
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"sclk_decon_eclk_disp",
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"sclk_decon_tv_vclk_disp",
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"aclk_disp_333";
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clocks = <&xxti>,
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<&cmu_mif CLK_SCLK_DSIM1_DISP>,
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<&cmu_mif CLK_SCLK_DSIM0_DISP>,
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<&cmu_mif CLK_SCLK_DSD_DISP>,
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<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
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<&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
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<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
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<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
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<&cmu_mif CLK_ACLK_DISP_333>;
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power-domains = <&pd_disp>;
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};
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cmu_aud: clock-controller@114c0000 {
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compatible = "samsung,exynos5433-cmu-aud";
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reg = <0x114c0000 0x0b04>;
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#clock-cells = <1>;
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clock-names = "oscclk", "fout_aud_pll";
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clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
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power-domains = <&pd_aud>;
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};
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cmu_bus0: clock-controller@13600000 {
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compatible = "samsung,exynos5433-cmu-bus0";
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reg = <0x13600000 0x0b04>;
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#clock-cells = <1>;
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clock-names = "aclk_bus0_400";
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clocks = <&cmu_top CLK_ACLK_BUS0_400>;
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};
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cmu_bus1: clock-controller@14800000 {
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compatible = "samsung,exynos5433-cmu-bus1";
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reg = <0x14800000 0x0b04>;
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#clock-cells = <1>;
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clock-names = "aclk_bus1_400";
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clocks = <&cmu_top CLK_ACLK_BUS1_400>;
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};
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cmu_bus2: clock-controller@13400000 {
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compatible = "samsung,exynos5433-cmu-bus2";
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reg = <0x13400000 0x0b04>;
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#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "aclk_bus2_400";
|
||
|
|
clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_g3d: clock-controller@14aa0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-g3d";
|
||
|
|
reg = <0x14aa0000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "aclk_g3d_400";
|
||
|
|
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
|
||
|
|
power-domains = <&pd_g3d>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_gscl: clock-controller@13cf0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-gscl";
|
||
|
|
reg = <0x13cf0000 0x0b10>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"aclk_gscl_111",
|
||
|
|
"aclk_gscl_333";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_top CLK_ACLK_GSCL_111>,
|
||
|
|
<&cmu_top CLK_ACLK_GSCL_333>;
|
||
|
|
power-domains = <&pd_gscl>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_apollo: clock-controller@11900000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-apollo";
|
||
|
|
reg = <0x11900000 0x1088>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "sclk_bus_pll_apollo";
|
||
|
|
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_atlas: clock-controller@11800000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-atlas";
|
||
|
|
reg = <0x11800000 0x1088>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "sclk_bus_pll_atlas";
|
||
|
|
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_mscl: clock-controller@105d0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-mscl";
|
||
|
|
reg = <0x105d0000 0x0b10>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"sclk_jpeg_mscl",
|
||
|
|
"aclk_mscl_400";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_top CLK_SCLK_JPEG_MSCL>,
|
||
|
|
<&cmu_top CLK_ACLK_MSCL_400>;
|
||
|
|
power-domains = <&pd_mscl>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_mfc: clock-controller@15280000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-mfc";
|
||
|
|
reg = <0x15280000 0x0b08>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "aclk_mfc_400";
|
||
|
|
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
|
||
|
|
power-domains = <&pd_mfc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_hevc: clock-controller@14f80000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-hevc";
|
||
|
|
reg = <0x14f80000 0x0b08>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk", "aclk_hevc_400";
|
||
|
|
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
|
||
|
|
power-domains = <&pd_hevc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_isp: clock-controller@146d0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-isp";
|
||
|
|
reg = <0x146d0000 0x0b0c>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"aclk_isp_dis_400",
|
||
|
|
"aclk_isp_400";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_top CLK_ACLK_ISP_DIS_400>,
|
||
|
|
<&cmu_top CLK_ACLK_ISP_400>;
|
||
|
|
power-domains = <&pd_isp>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_cam0: clock-controller@120d0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-cam0";
|
||
|
|
reg = <0x120d0000 0x0b0c>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"aclk_cam0_333",
|
||
|
|
"aclk_cam0_400",
|
||
|
|
"aclk_cam0_552";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM0_333>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM0_400>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM0_552>;
|
||
|
|
power-domains = <&pd_cam0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmu_cam1: clock-controller@145d0000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-cam1";
|
||
|
|
reg = <0x145d0000 0x0b08>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"sclk_isp_uart_cam1",
|
||
|
|
"sclk_isp_spi1_cam1",
|
||
|
|
"sclk_isp_spi0_cam1",
|
||
|
|
"aclk_cam1_333",
|
||
|
|
"aclk_cam1_400",
|
||
|
|
"aclk_cam1_552";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_top CLK_SCLK_ISP_UART_CAM1>,
|
||
|
|
<&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
|
||
|
|
<&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM1_333>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM1_400>,
|
||
|
|
<&cmu_top CLK_ACLK_CAM1_552>;
|
||
|
|
power-domains = <&pd_cam1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
Example 3: UART controller node that consumes the clock generated by the clock
|
||
|
|
controller.
|
||
|
|
|
||
|
|
serial_0: serial@14c10000 {
|
||
|
|
compatible = "samsung,exynos5433-uart";
|
||
|
|
reg = <0x14C10000 0x100>;
|
||
|
|
interrupts = <0 421 0>;
|
||
|
|
clocks = <&cmu_peric CLK_PCLK_UART0>,
|
||
|
|
<&cmu_peric CLK_SCLK_UART0>;
|
||
|
|
clock-names = "uart", "clk_uart_baud0";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&uart0_bus>;
|
||
|
|
};
|