84 lines
2.6 KiB
Plaintext
84 lines
2.6 KiB
Plaintext
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Broadcom STB "UPG GIO" GPIO controller
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The controller's registers are organized as sets of eight 32-bit
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registers with each set controlling a bank of up to 32 pins. A single
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interrupt is shared for all of the banks handled by the controller.
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Required properties:
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- compatible:
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Must be "brcm,brcmstb-gpio"
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- reg:
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Define the base and range of the I/O address space containing
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the brcmstb GPIO controller registers
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- #gpio-cells:
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Should be <2>. The first cell is the pin number (within the controller's
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pin space), and the second is used for the following:
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bit[0]: polarity (0 for active-high, 1 for active-low)
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- gpio-controller:
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Specifies that the node is a GPIO controller.
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- brcm,gpio-bank-widths:
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Number of GPIO lines for each bank. Number of elements must
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correspond to number of banks suggested by the 'reg' property.
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Optional properties:
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- interrupts:
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The interrupt shared by all GPIO lines for this controller.
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- interrupts-extended:
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Alternate form of specifying interrupts and parents that allows for
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multiple parents. This takes precedence over 'interrupts' and
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'interrupt-parent'. Wakeup-capable GPIO controllers often route their
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wakeup interrupt lines through a different interrupt controller than the
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primary interrupt line, making this property necessary.
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- #interrupt-cells:
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Should be <2>. The first cell is the GPIO number, the second should specify
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flags. The following subset of flags is supported:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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Valid combinations are 1, 2, 3, 4, 8.
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See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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- interrupt-controller:
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Marks the device node as an interrupt controller
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- wakeup-source:
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GPIOs for this controller can be used as a wakeup source
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Example:
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upg_gio: gpio@f040a700 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf040a700 0x80>;
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interrupt-parent = <&irq0_intc>;
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interrupts = <0x6>;
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brcm,gpio-bank-widths = <32 32 32 24>;
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};
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upg_gio_aon: gpio@f04172c0 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf04172c0 0x40>;
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interrupt-parent = <&irq0_aon_intc>;
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interrupts = <0x6>;
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interrupts-extended = <&irq0_aon_intc 0x6>,
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<&aon_pm_l2_intc 0x5>;
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wakeup-source;
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brcm,gpio-bank-widths = <18 4>;
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};
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