31 lines
993 B
Plaintext
31 lines
993 B
Plaintext
|
* Renesas VSP Video Processing Engine
|
||
|
|
|
||
|
|
The VSP is a video processing engine that supports up-/down-scaling, alpha
|
||
|
|
blending, color space conversion and various other image processing features.
|
||
|
|
It can be found in the Renesas R-Car second generation SoCs.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
|
||
|
|
- compatible: Must contain one of the following values
|
||
|
|
- "renesas,vsp1" for the R-Car Gen2 VSP1
|
||
|
|
- "renesas,vsp2" for the R-Car Gen3 VSP2
|
||
|
|
|
||
|
|
- reg: Base address and length of the registers block for the VSP.
|
||
|
|
- interrupts: VSP interrupt specifier.
|
||
|
|
- clocks: A phandle + clock-specifier pair for the VSP functional clock.
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
|
||
|
|
- renesas,fcp: A phandle referencing the FCP that handles memory accesses
|
||
|
|
for the VSP. Not needed on Gen2, mandatory on Gen3.
|
||
|
|
|
||
|
|
|
||
|
|
Example: R8A7790 (R-Car H2) VSP1-S node
|
||
|
|
|
||
|
|
vsp@fe928000 {
|
||
|
|
compatible = "renesas,vsp1";
|
||
|
|
reg = <0 0xfe928000 0 0x8000>;
|
||
|
|
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||
|
|
};
|