67 lines
2.6 KiB
Plaintext
67 lines
2.6 KiB
Plaintext
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XICS interrupt controller
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Device type supported: KVM_DEV_TYPE_XICS
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Groups:
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KVM_DEV_XICS_SOURCES
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Attributes: One per interrupt source, indexed by the source number.
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This device emulates the XICS (eXternal Interrupt Controller
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Specification) defined in PAPR. The XICS has a set of interrupt
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sources, each identified by a 20-bit source number, and a set of
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Interrupt Control Presentation (ICP) entities, also called "servers",
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each associated with a virtual CPU.
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The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH
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capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
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the interrupt server number (i.e. the vcpu number from the XICS's
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point of view) in args[1] of the kvm_enable_cap struct. Each ICP has
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64 bits of state which can be read and written using the
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KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
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state word has the following bitfields, starting at the
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least-significant end of the word:
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* Unused, 16 bits
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* Pending interrupt priority, 8 bits
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Zero is the highest priority, 255 means no interrupt is pending.
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* Pending IPI (inter-processor interrupt) priority, 8 bits
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Zero is the highest priority, 255 means no IPI is pending.
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* Pending interrupt source number, 24 bits
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Zero means no interrupt pending, 2 means an IPI is pending
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* Current processor priority, 8 bits
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Zero is the highest priority, meaning no interrupts can be
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delivered, and 255 is the lowest priority.
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Each source has 64 bits of state that can be read and written using
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the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the
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KVM_DEV_XICS_SOURCES attribute group, with the attribute number being
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the interrupt source number. The 64 bit state word has the following
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bitfields, starting from the least-significant end of the word:
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* Destination (server number), 32 bits
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This specifies where the interrupt should be sent, and is the
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interrupt server number specified for the destination vcpu.
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* Priority, 8 bits
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This is the priority specified for this interrupt source, where 0 is
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the highest priority and 255 is the lowest. An interrupt with a
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priority of 255 will never be delivered.
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* Level sensitive flag, 1 bit
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This bit is 1 for a level-sensitive interrupt source, or 0 for
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edge-sensitive (or MSI).
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* Masked flag, 1 bit
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This bit is set to 1 if the interrupt is masked (cannot be delivered
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regardless of its priority), for example by the ibm,int-off RTAS
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call, or 0 if it is not masked.
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* Pending flag, 1 bit
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This bit is 1 if the source has a pending interrupt, otherwise 0.
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Only one XICS instance may be created per VM.
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