378 lines
12 KiB
C
378 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* include/asm-alpha/dma.h
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*
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* This is essentially the same as the i386 DMA stuff, as the AlphaPCs
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* use ISA-compatible dma. The only extension is support for high-page
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* registers that allow to set the top 8 bits of a 32-bit DMA address.
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* This register should be written last when setting up a DMA address
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* as this will also enable DMA across 64 KB boundaries.
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*/
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/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
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* linux/include/asm/dma.h: Defines for using and allocating dma channels.
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* Written by Hennus Bergman, 1992.
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* High DMA channel support & info by Hannu Savolainen
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* and John Boyd, Nov. 1992.
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*/
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#ifndef _ASM_DMA_H
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#define _ASM_DMA_H
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#define dma_outb outb
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#define dma_inb inb
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/*
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* NOTES about DMA transfers:
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*
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* controller 1: channels 0-3, byte operations, ports 00-1F
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* controller 2: channels 4-7, word operations, ports C0-DF
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*
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* - ALL registers are 8 bits only, regardless of transfer size
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* - channel 4 is not used - cascades 1 into 2.
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* - channels 0-3 are byte - addresses/counts are for physical bytes
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* - channels 5-7 are word - addresses/counts are for physical words
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* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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* - transfer count loaded to registers is 1 less than actual count
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* - controller 2 offsets are all even (2x offsets for controller 1)
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* - page registers for 5-7 don't use data bit 0, represent 128K pages
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* - page registers for 0-3 use bit 0, represent 64K pages
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*
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* DMA transfers are limited to the lower 16MB of _physical_ memory.
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* Note that addresses loaded into registers must be _physical_ addresses,
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* not logical addresses (which may differ if paging is active).
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*
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* Address mapping for channels 0-3:
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*
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* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* P7 ... P0 A7 ... A0 A7 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Address mapping for channels 5-7:
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*
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* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
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* | ... | \ \ ... \ \ \ ... \ \
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* | ... | \ \ ... \ \ \ ... \ (not used)
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* | ... | \ \ ... \ \ \ ... \
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* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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* the hardware level, so odd-byte transfers aren't possible).
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*
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* Transfer count (_not # bytes_) is limited to 64K, represented as actual
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* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
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* and up to 128K bytes may be transferred on channels 5-7 in one operation.
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*
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*/
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#define MAX_DMA_CHANNELS 8
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/*
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ISA DMA limitations on Alpha platforms,
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These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
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just a wiring limit.
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*/
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/* The maximum address for ISA DMA transfer on Alpha XL, due to an
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hardware SIO limitation, is 64MB.
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*/
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#define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL
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/* The maximum address for ISA DMA transfer on RUFFIAN,
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due to an hardware SIO limitation, is 16MB.
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*/
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#define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL
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/* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
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due to an hardware SIO chip limitation, is 2GB.
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*/
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#define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL
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#define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL
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/*
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Maximum address for all the others is the complete 32-bit bus
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address space.
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*/
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#define ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL
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#ifdef CONFIG_ALPHA_GENERIC
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# define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address)
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#else
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# if defined(CONFIG_ALPHA_XL)
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# define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS
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# elif defined(CONFIG_ALPHA_RUFFIAN)
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# define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
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# elif defined(CONFIG_ALPHA_SABLE)
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# define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
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# elif defined(CONFIG_ALPHA_ALCOR)
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# define MAX_ISA_DMA_ADDRESS ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
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# else
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# define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS
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# endif
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#endif
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/* If we have the iommu, we don't have any address limitations on DMA.
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Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
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like i386. */
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#define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \
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~0UL : IDENT_ADDR + 0x01000000)
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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#define DMA1_MODE_REG 0x0B /* mode register (w) */
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
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#define DMA2_CMD_REG 0xD0 /* command register (w) */
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#define DMA2_STAT_REG 0xD0 /* status register (r) */
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#define DMA2_REQ_REG 0xD2 /* request register (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
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#define DMA_ADDR_0 0x00 /* DMA address registers */
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#define DMA_ADDR_1 0x02
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#define DMA_ADDR_2 0x04
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#define DMA_ADDR_3 0x06
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#define DMA_ADDR_4 0xC0
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#define DMA_ADDR_5 0xC4
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#define DMA_ADDR_6 0xC8
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#define DMA_ADDR_7 0xCC
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#define DMA_CNT_0 0x01 /* DMA count registers */
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#define DMA_CNT_1 0x03
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#define DMA_CNT_2 0x05
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#define DMA_CNT_3 0x07
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#define DMA_CNT_4 0xC2
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#define DMA_CNT_5 0xC6
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#define DMA_CNT_6 0xCA
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#define DMA_CNT_7 0xCE
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#define DMA_PAGE_0 0x87 /* DMA page registers */
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#define DMA_PAGE_1 0x83
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#define DMA_PAGE_2 0x81
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#define DMA_PAGE_3 0x82
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#define DMA_PAGE_5 0x8B
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#define DMA_PAGE_6 0x89
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#define DMA_PAGE_7 0x8A
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#define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
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#define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
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#define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
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#define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
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#define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
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#define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
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#define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
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#define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr, DMA1_MASK_REG);
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else
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dma_outb(dmanr & 3, DMA2_MASK_REG);
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr | 4, DMA1_MASK_REG);
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else
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dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while interrupts are disabled! ---
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(0, DMA1_CLEAR_FF_REG);
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else
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dma_outb(0, DMA2_CLEAR_FF_REG);
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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if (dmanr<=3)
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dma_outb(mode | dmanr, DMA1_MODE_REG);
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else
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dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
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}
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/* set extended mode for a specific DMA channel */
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static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
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{
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if (dmanr<=3)
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dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
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else
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dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
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}
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/* Set only the page register bits of the transfer address.
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* This is used for successive transfers when we know the contents of
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* the lower 16 bits of the DMA current address register.
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*/
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static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
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{
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switch(dmanr) {
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case 0:
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dma_outb(pagenr, DMA_PAGE_0);
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dma_outb((pagenr >> 8), DMA_HIPAGE_0);
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break;
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case 1:
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dma_outb(pagenr, DMA_PAGE_1);
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dma_outb((pagenr >> 8), DMA_HIPAGE_1);
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break;
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case 2:
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dma_outb(pagenr, DMA_PAGE_2);
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dma_outb((pagenr >> 8), DMA_HIPAGE_2);
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break;
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case 3:
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dma_outb(pagenr, DMA_PAGE_3);
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dma_outb((pagenr >> 8), DMA_HIPAGE_3);
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break;
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case 5:
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dma_outb(pagenr & 0xfe, DMA_PAGE_5);
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dma_outb((pagenr >> 8), DMA_HIPAGE_5);
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break;
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case 6:
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dma_outb(pagenr & 0xfe, DMA_PAGE_6);
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dma_outb((pagenr >> 8), DMA_HIPAGE_6);
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break;
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case 7:
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dma_outb(pagenr & 0xfe, DMA_PAGE_7);
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dma_outb((pagenr >> 8), DMA_HIPAGE_7);
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break;
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}
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}
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/* Set transfer address & page bits for specific DMA channel.
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* Assumes dma flipflop is clear.
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*/
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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if (dmanr <= 3) {
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dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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} else {
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dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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}
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set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
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}
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/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
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* a specific DMA channel.
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* You must ensure the parameters are valid.
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* NOTE: from a manual: "the number of transfers is one more
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* than the initial word count"! This is taken into account.
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* Assumes dma flip-flop is clear.
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* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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count--;
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if (dmanr <= 3) {
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dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
|
||
|
|
} else {
|
||
|
|
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
|
||
|
|
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* Get DMA residue count. After a DMA transfer, this
|
||
|
|
* should return zero. Reading this while a DMA transfer is
|
||
|
|
* still in progress will return unpredictable results.
|
||
|
|
* If called before the channel has been used, it may return 1.
|
||
|
|
* Otherwise, it returns the number of _bytes_ left to transfer.
|
||
|
|
*
|
||
|
|
* Assumes DMA flip-flop is clear.
|
||
|
|
*/
|
||
|
|
static __inline__ int get_dma_residue(unsigned int dmanr)
|
||
|
|
{
|
||
|
|
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
|
||
|
|
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
|
||
|
|
|
||
|
|
/* using short to get 16-bit wrap around */
|
||
|
|
unsigned short count;
|
||
|
|
|
||
|
|
count = 1 + dma_inb(io_port);
|
||
|
|
count += dma_inb(io_port) << 8;
|
||
|
|
|
||
|
|
return (dmanr<=3)? count : (count<<1);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* These are in kernel/dma.c: */
|
||
|
|
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
|
||
|
|
extern void free_dma(unsigned int dmanr); /* release it again */
|
||
|
|
#define KERNEL_HAVE_CHECK_DMA
|
||
|
|
extern int check_dma(unsigned int dmanr);
|
||
|
|
|
||
|
|
/* From PCI */
|
||
|
|
|
||
|
|
#ifdef CONFIG_PCI
|
||
|
|
extern int isa_dma_bridge_buggy;
|
||
|
|
#else
|
||
|
|
#define isa_dma_bridge_buggy (0)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* _ASM_DMA_H */
|