305 lines
8 KiB
ArmAsm
305 lines
8 KiB
ArmAsm
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/*
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* ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
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#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
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#include <asm/errno.h>
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#include <asm/arcregs.h>
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#include <asm/irqflags.h>
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; A maximum number of supported interrupts in the core interrupt controller.
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; This number is not equal to the maximum interrupt number (256) because
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; first 16 lines are reserved for exceptions and are not configurable.
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#define NR_CPU_IRQS 240
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.cpu HS
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#define VECTOR .word
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;############################ Vector Table #################################
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.section .vector,"a",@progbits
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.align 4
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# Initial 16 slots are Exception Vectors
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VECTOR res_service ; Reset Vector
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VECTOR mem_service ; Mem exception
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VECTOR instr_service ; Instrn Error
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VECTOR EV_MachineCheck ; Fatal Machine check
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VECTOR EV_TLBMissI ; Intruction TLB miss
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VECTOR EV_TLBMissD ; Data TLB miss
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VECTOR EV_TLBProtV ; Protection Violation
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VECTOR EV_PrivilegeV ; Privilege Violation
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VECTOR EV_SWI ; Software Breakpoint
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VECTOR EV_Trap ; Trap exception
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VECTOR EV_Extension ; Extn Instruction Exception
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VECTOR EV_DivZero ; Divide by Zero
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VECTOR EV_DCError ; Data Cache Error
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VECTOR EV_Misaligned ; Misaligned Data Access
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VECTOR reserved ; Reserved slots
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VECTOR reserved ; Reserved slots
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# Begin Interrupt Vectors
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VECTOR handle_interrupt ; (16) Timer0
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VECTOR handle_interrupt ; unused (Timer1)
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VECTOR handle_interrupt ; unused (WDT)
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VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
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VECTOR handle_interrupt ; (20) perf Interrupt
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VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
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VECTOR handle_interrupt ; unused
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VECTOR handle_interrupt ; (23) unused
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# End of fixed IRQs
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.rept NR_CPU_IRQS - 8
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VECTOR handle_interrupt
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.endr
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.section .text, "ax",@progbits
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reserved:
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flag 1 ; Unexpected event, halt
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;##################### Interrupt Handling ##############################
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ENTRY(handle_interrupt)
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INTERRUPT_PROLOGUE irq
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# irq control APIs local_irq_save/restore/disable/enable fiddle with
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# global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
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# However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
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# query in hard ISR path would return false (since .IE is set) which would
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# trips genirq interrupt handling asserts.
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#
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# So do a "soft" disable of interrutps here.
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#
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# Note this disable is only for consistent book-keeping as further interrupts
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# will be disabled anyways even w/o this. Hardware tracks active interrupts
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# seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts
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# unless this one returns (or higher prio becomes pending in 2-prio scheme)
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IRQ_DISABLE
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; icause is banked: one per priority level
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; so a higher prio interrupt taken here won't clobber prev prio icause
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lr r0, [ICAUSE]
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mov blink, ret_from_exception
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b.d arch_do_IRQ
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mov r1, sp
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END(handle_interrupt)
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;################### Non TLB Exception Handling #############################
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ENTRY(EV_SWI)
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; TODO: implement this
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EXCEPTION_PROLOGUE
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b ret_from_exception
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END(EV_SWI)
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ENTRY(EV_DivZero)
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; TODO: implement this
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EXCEPTION_PROLOGUE
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b ret_from_exception
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END(EV_DivZero)
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ENTRY(EV_DCError)
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; TODO: implement this
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EXCEPTION_PROLOGUE
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b ret_from_exception
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END(EV_DCError)
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; ---------------------------------------------
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; Memory Error Exception Handler
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; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
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; Instruction fetch or Data access, under a single Exception Vector
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; ---------------------------------------------
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ENTRY(mem_service)
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN
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bl do_memory_error
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b ret_from_exception
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END(mem_service)
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ENTRY(EV_Misaligned)
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EXCEPTION_PROLOGUE
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lr r0, [efa] ; Faulting Data address
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mov r1, sp
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FAKE_RET_FROM_EXCPN
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SAVE_CALLEE_SAVED_USER
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mov r2, sp ; callee_regs
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bl do_misaligned_access
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; TBD: optimize - do this only if a callee reg was involved
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; either a dst of emulated LD/ST or src with address-writeback
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RESTORE_CALLEE_SAVED_USER
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b ret_from_exception
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END(EV_Misaligned)
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; ---------------------------------------------
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; Protection Violation Exception Handler
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; ---------------------------------------------
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ENTRY(EV_TLBProtV)
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EXCEPTION_PROLOGUE
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lr r0, [efa] ; Faulting Data address
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mov r1, sp ; pt_regs
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FAKE_RET_FROM_EXCPN
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mov blink, ret_from_exception
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b do_page_fault
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END(EV_TLBProtV)
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; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
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; need to call do_page_fault().
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; ECR in pt_regs provides whether access was R/W/X
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.global call_do_page_fault
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.set call_do_page_fault, EV_TLBProtV
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;############# Common Handlers for ARCompact and ARCv2 ##############
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#include "entry.S"
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;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
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;
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; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
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; IRQ shd definitely not happen between now and rtie
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; All 2 entry points to here already disable interrupts
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.Lrestore_regs:
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restore_regs:
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# Interrpts are actually disabled from this point on, but will get
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# reenabled after we return from interrupt/exception.
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# But irq tracer needs to be told now...
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TRACE_ASM_IRQ_ENABLE
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ld r0, [sp, PT_status32] ; U/K mode at time of entry
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lr r10, [AUX_IRQ_ACT]
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bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE
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breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
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;####### Return from Intr #######
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debug_marker_l1:
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; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
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btst r0, STATUS_DE_BIT ; Z flag set if bit clear
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bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
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.Lisr_ret_fast_path:
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; Handle special case #1: (Entry via Exception, Return via IRQ)
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;
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; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
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; task now returning to U mode (riding the Intr)
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; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
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; won't be switched to correct U mode value (from AUX_SP)
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; So force AUX_IRQ_ACT.U for such a case
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btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
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bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
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sr r11, [AUX_IRQ_ACT]
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INTERRUPT_EPILOGUE irq
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rtie
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;####### Return from Exception / pure kernel mode #######
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.Lexcept_ret: ; Expects r0 has PT_status32
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debug_marker_syscall:
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EXCEPTION_EPILOGUE
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rtie
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;####### Return from Intr to insn in delay slot #######
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; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
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;
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; Intr returning to a Delay Slot (DS) insn
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; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
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; entry was via Exception in DS which got preempted in kernel).
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;
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; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
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;
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; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
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; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
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.Lintr_ret_to_delay_slot:
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debug_marker_ds:
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ld r2, [@intr_to_DE_cnt]
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add r2, r2, 1
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st r2, [@intr_to_DE_cnt]
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ld r2, [sp, PT_ret]
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ld r3, [sp, PT_status32]
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; STAT32 for Int return created from scratch
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; (No delay dlot, disable Further intr in trampoline)
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bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
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st r0, [sp, PT_status32]
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mov r1, .Lintr_ret_to_delay_slot_2
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st r1, [sp, PT_ret]
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; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
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st r2, [sp, 0]
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st r3, [sp, 4]
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b .Lisr_ret_fast_path
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.Lintr_ret_to_delay_slot_2:
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; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
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sub sp, sp, SZ_PT_REGS
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st r9, [sp, -4]
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ld r9, [sp, 0]
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sr r9, [eret]
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ld r9, [sp, 4]
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sr r9, [erstatus]
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; restore AUX_USER_SP if returning to U mode
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bbit0 r9, STATUS_U_BIT, 1f
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ld r9, [sp, PT_sp]
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sr r9, [AUX_USER_SP]
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1:
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ld r9, [sp, 8]
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sr r9, [erbta]
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ld r9, [sp, -4]
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add sp, sp, SZ_PT_REGS
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; return from pure kernel mode to delay slot
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rtie
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END(ret_from_exception)
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