70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
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/*
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* at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
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* 4 USART.
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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serial4 = &usart3;
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};
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ahb {
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apb {
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pinctrl@fffff400 {
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usart3 {
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pinctrl_usart3: usart3-0 {
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atmel,pins =
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<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE
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AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
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};
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
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};
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pinctrl_usart3_sck: usart3_sck-0 {
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atmel,pins =
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<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
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};
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};
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};
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pmc: pmc@fffffc00 {
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periphck {
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usart3_clk: usart3_clk {
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#clock-cells = <0>;
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reg = <8>;
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};
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};
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};
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usart3: serial@f8028000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8028000 0x200>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart3>;
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dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
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<&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
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dma-names = "tx", "rx";
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clocks = <&usart3_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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};
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};
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};
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