286 lines
6.7 KiB
Plaintext
286 lines
6.7 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the EMEV2 SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,emev2";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &iic0;
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i2c1 = &iic1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <533000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <533000000>;
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};
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};
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gic: interrupt-controller@e0020000 {
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compatible = "arm,pl390";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xe0028000 0x1000>,
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<0xe0020000 0x0100>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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clocks@e0110000 {
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compatible = "renesas,emev2-smu";
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reg = <0xe0110000 0x10000>;
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#address-cells = <2>;
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#size-cells = <0>;
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c32ki: c32ki {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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iic0_sclkdiv: iic0_sclkdiv@624,0 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x624 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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iic0_sclk: iic0_sclk@48c,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x48c 1>;
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clocks = <&iic0_sclkdiv>;
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#clock-cells = <0>;
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};
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iic1_sclkdiv: iic1_sclkdiv@624,16 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x624 16>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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iic1_sclk: iic1_sclk@490,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x490 1>;
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clocks = <&iic1_sclkdiv>;
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#clock-cells = <0>;
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};
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pll3_fo: pll3_fo {
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compatible = "fixed-factor-clock";
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clocks = <&c32ki>;
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clock-div = <1>;
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clock-mult = <7000>;
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#clock-cells = <0>;
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};
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usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x65c 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x65c 16>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x660 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk@4a0,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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usib_u1_sclk: usib_u1_sclk@4b8,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4b8 1>;
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clocks = <&usib_u1_sclkdiv>;
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#clock-cells = <0>;
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};
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usib_u2_sclk: usib_u2_sclk@4bc,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4bc 1>;
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clocks = <&usib_u2_sclkdiv>;
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#clock-cells = <0>;
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};
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usib_u3_sclk: usib_u3_sclk@4c0,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4c0 1>;
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clocks = <&usib_u3_sclkdiv>;
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#clock-cells = <0>;
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};
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sti_sclk: sti_sclk@528,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x528 1>;
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clocks = <&c32ki>;
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#clock-cells = <0>;
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};
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};
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timer@e0180000 {
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compatible = "renesas,em-sti";
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reg = <0xe0180000 0x54>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sti_sclk>;
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clock-names = "sclk";
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};
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uart0: serial@e1020000 {
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compatible = "renesas,em-uart";
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reg = <0xe1020000 0x38>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usia_u0_sclk>;
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clock-names = "sclk";
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};
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uart1: serial@e1030000 {
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compatible = "renesas,em-uart";
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reg = <0xe1030000 0x38>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usib_u1_sclk>;
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clock-names = "sclk";
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};
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uart2: serial@e1040000 {
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compatible = "renesas,em-uart";
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reg = <0xe1040000 0x38>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usib_u2_sclk>;
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clock-names = "sclk";
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};
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uart3: serial@e1050000 {
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compatible = "renesas,em-uart";
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reg = <0xe1050000 0x38>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usib_u3_sclk>;
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clock-names = "sclk";
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};
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pfc: pin-controller@e0140200 {
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compatible = "renesas,pfc-emev2";
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reg = <0xe0140200 0x100>;
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};
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gpio0: gpio@e0050000 {
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compatible = "renesas,em-gio";
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reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@e0050080 {
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compatible = "renesas,em-gio";
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reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@e0050100 {
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compatible = "renesas,em-gio";
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reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@e0050180 {
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compatible = "renesas,em-gio";
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reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@e0050200 {
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compatible = "renesas,em-gio";
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reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 31>;
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#gpio-cells = <2>;
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ngpios = <31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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iic0: i2c@e0070000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-emev2";
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reg = <0xe0070000 0x28>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
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clocks = <&iic0_sclk>;
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clock-names = "sclk";
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status = "disabled";
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};
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iic1: i2c@e10a0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-emev2";
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reg = <0xe10a0000 0x28>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
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clocks = <&iic1_sclk>;
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clock-names = "sclk";
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status = "disabled";
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};
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};
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