337 lines
9.7 KiB
Plaintext
337 lines
9.7 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a77470 SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
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/ {
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compatible = "renesas,r8a77470";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
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power-domains = <&sysc 5>;
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next-level-cache = <&L2_CA7>;
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};
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L2_CA7: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc 21>;
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};
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};
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/* External root clock */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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/* External SCIF clock */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77470-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77470-rst";
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reg = <0 0xe6160000 0 0x100>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77470-sysc";
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reg = <0 0xe6180000 0 0x200>;
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#power-domain-cells = <1>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a77470", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc 32>;
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resets = <&cpg 407>;
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};
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icram0: sram@e63a0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63a0000 0 0x12000>;
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};
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icram1: sram@e63c0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63c0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63c0000 0x1000>;
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smp-sram@0 {
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compatible = "renesas,smp-sram";
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reg = <0 0x100>;
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};
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};
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icram2: sram@e6300000 {
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compatible = "mmio-sram";
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reg = <0 0xe6300000 0 0x20000>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a77470",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 219>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a77470",
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"renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77470",
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"renesas,etheravb-rcar-gen2";
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reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc 32>;
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resets = <&cpg 812>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e60000 0 0x40>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 721>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
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<&dmac1 0x29>, <&dmac1 0x2a>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 721>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e68000 0 0x40>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 720>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
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<&dmac1 0x2d>, <&dmac1 0x2e>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 720>;
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status = "disabled";
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};
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scif2: serial@e6e58000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e58000 0 0x40>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 719>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
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<&dmac1 0x2b>, <&dmac1 0x2c>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 719>;
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status = "disabled";
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};
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scif3: serial@e6ea8000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6ea8000 0 0x40>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 718>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
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<&dmac1 0x2f>, <&dmac1 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 718>;
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status = "disabled";
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};
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scif4: serial@e6ee0000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6ee0000 0 0x40>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 715>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
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<&dmac1 0xfb>, <&dmac1 0xfc>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 715>;
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status = "disabled";
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};
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scif5: serial@e6ee8000 {
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compatible = "renesas,scif-r8a77470",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6ee8000 0 0x40>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 714>,
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<&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
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<&dmac1 0xfd>, <&dmac1 0xfe>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 714>;
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status = "disabled";
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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resets = <&cpg 408>;
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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||
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* External USB clock - can be overridden by the board */
|
||
|
|
usb_extal_clk: usb_extal {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <48000000>;
|
||
|
|
};
|
||
|
|
};
|