90 lines
2 KiB
Plaintext
90 lines
2 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron (and derivatives) fragment for sdmmc cards
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*
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* Copyright 2015 Google, Inc
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*/
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&io_domains {
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sdcard-supply = <&vccio_sd>;
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};
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&pinctrl {
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sdmmc {
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/*
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* We run sdmmc at max speed; bump up drive strength.
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* We also have external pulls, so disable the internal ones.
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*/
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
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<6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
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<6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
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<6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
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};
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sdmmc_clk: sdmmc-clk {
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rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
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};
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/*
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* Builtin CD line is hooked to ground to prevent JTAG at boot
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* (and also to get the voltage rail correct).
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* Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
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* think there's a card inserted
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*/
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sdmmc_cd_disabled: sdmmc-cd-disabled {
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rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/* This is where we actually hook up CD */
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sdmmc_cd_gpio: sdmmc-cd-gpio {
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rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&rk808 {
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vcc9-supply = <&vcc_5v>;
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regulators {
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vccio_sd: LDO_REG4 {
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regulator-name = "vccio_sd";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc33_sd: LDO_REG5 {
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regulator-name = "vcc33_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdmmc {
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status = "okay";
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc33_sd>;
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vqmmc-supply = <&vccio_sd>;
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};
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