562 lines
15 KiB
Plaintext
562 lines
15 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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#include "tegra20.dtsi"
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/ {
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model = "Toradex Colibri T20 256/512 MB";
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compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
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aliases {
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rtc0 = "/i2c@7000d000/tps6586x@34";
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rtc1 = "/rtc@7000e000";
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};
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memory@0 {
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/*
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* Set memory to 256 MB to be safe as this could be used on
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* 256 or 512 MB module. It is expected from bootloader
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* to fix this up for 512 MB version.
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*/
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reg = <0x00000000 0x10000000>;
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};
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host1x@50000000 {
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hdmi@54280000 {
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&i2c_ddc>;
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
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GPIO_ACTIVE_HIGH>;
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};
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};
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pinmux@70000014 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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audio_refclk {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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crt {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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displaya {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3",
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"ld4", "ld5", "ld6", "ld7", "ld8",
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"ld9", "ld10", "ld11", "ld12", "ld13",
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"ld14", "ld15", "ld16", "ld17",
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"lhs", "lpw0", "lpw2", "lsc0",
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"lsc1", "lsck", "lsda", "lspi", "lvs";
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nvidia,function = "displaya";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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gpio_dte {
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nvidia,pins = "dte";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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gpio_gmi {
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nvidia,pins = "ata", "atc", "atd", "ate",
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"dap1", "dap2", "dap4", "gpu", "irrx",
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"irtx", "spia", "spib", "spic";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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gpio_pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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gpio_uac {
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nvidia,pins = "uac";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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hdint {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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i2c1 {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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i2c3 {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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i2cddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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irda {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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nand {
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nvidia,pins = "kbca", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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owc {
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nvidia,pins = "owc";
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nvidia,function = "owr";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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pwm {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "pwm";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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sdio4 {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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spi1 {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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spi4 {
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nvidia,pins = "slxa", "slxc", "slxd", "slxk";
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nvidia,function = "spi4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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uarta {
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nvidia,pins = "sdio1";
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nvidia,function = "uarta";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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uartd {
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nvidia,pins = "gmc";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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ulpi {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_refclk {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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usb_gpio {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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vi {
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nvidia,pins = "dta", "dtb", "dtc", "dtd";
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nvidia,function = "vi";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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vi_sc {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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ac97: ac97@70002000 {
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status = "okay";
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nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
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GPIO_ACTIVE_HIGH>;
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nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
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GPIO_ACTIVE_HIGH>;
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};
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nand-controller@70008000 {
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status = "okay";
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nand@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-bus-width = <8>;
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nand-on-flash-bbt;
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nand-ecc-algo = "bch";
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nand-is-boot-medium;
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nand-ecc-maximize;
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wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
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};
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};
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/*
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* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
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* board)
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*/
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i2c@7000c000 {
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clock-frequency = <400000>;
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};
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/* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
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i2c_ddc: i2c@7000c400 {
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clock-frequency = <10000>;
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};
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/* GEN2_I2C: unused */
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/* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
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/* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <100000>;
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pmic: tps6586x@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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ti,system-power-controller;
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#gpio-cells = <2>;
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gpio-controller;
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sys-supply = <&vdd_3v3_reg>;
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vin-sm0-supply = <&sys_reg>;
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vin-sm1-supply = <&sys_reg>;
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vin-sm2-supply = <&sys_reg>;
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vinldo01-supply = <&sm2_reg>;
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vinldo23-supply = <&vdd_3v3_reg>;
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vinldo4-supply = <&vdd_3v3_reg>;
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vinldo678-supply = <&vdd_3v3_reg>;
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vinldo9-supply = <&vdd_3v3_reg>;
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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sys_reg: regulator@0 {
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reg = <0>;
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regulator-compatible = "sys";
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regulator-name = "vdd_sys";
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regulator-always-on;
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};
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regulator@1 {
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reg = <1>;
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regulator-compatible = "sm0";
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regulator-name = "vdd_sm0,vdd_core";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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regulator@2 {
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reg = <2>;
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regulator-compatible = "sm1";
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regulator-name = "vdd_sm1,vdd_cpu";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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sm2_reg: regulator@3 {
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reg = <3>;
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regulator-compatible = "sm2";
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regulator-name = "vdd_sm2,vin_ldo*";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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/* LDO0 is not connected to anything */
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regulator@5 {
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reg = <5>;
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regulator-compatible = "ldo1";
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regulator-name = "vdd_ldo1,avdd_pll*";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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regulator@6 {
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reg = <6>;
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regulator-compatible = "ldo2";
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regulator-name = "vdd_ldo2,vdd_rtc";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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/* LDO3 is not connected to anything */
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regulator@8 {
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reg = <8>;
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regulator-compatible = "ldo4";
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regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo5_reg: regulator@9 {
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reg = <9>;
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regulator-compatible = "ldo5";
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regulator-name = "vdd_ldo5,vdd_fuse";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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regulator@10 {
|
||
|
|
reg = <10>;
|
||
|
|
regulator-compatible = "ldo6";
|
||
|
|
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
||
|
|
regulator-min-microvolt = <2850000>;
|
||
|
|
regulator-max-microvolt = <2850000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmi_vdd_reg: regulator@11 {
|
||
|
|
reg = <11>;
|
||
|
|
regulator-compatible = "ldo7";
|
||
|
|
regulator-name = "vdd_ldo7,avdd_hdmi";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmi_pll_reg: regulator@12 {
|
||
|
|
reg = <12>;
|
||
|
|
regulator-compatible = "ldo8";
|
||
|
|
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
regulator@13 {
|
||
|
|
reg = <13>;
|
||
|
|
regulator-compatible = "ldo9";
|
||
|
|
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||
|
|
regulator-min-microvolt = <2850000>;
|
||
|
|
regulator-max-microvolt = <2850000>;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
regulator@14 {
|
||
|
|
reg = <14>;
|
||
|
|
regulator-compatible = "ldo_rtc";
|
||
|
|
regulator-name = "vdd_rtc_out,vdd_cell";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
temperature-sensor@4c {
|
||
|
|
compatible = "national,lm95245";
|
||
|
|
reg = <0x4c>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmc@7000e400 {
|
||
|
|
nvidia,suspend-mode = <1>;
|
||
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
||
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
||
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
||
|
|
nvidia,core-pwr-off-time = <3875>;
|
||
|
|
nvidia,sys-clock-req-active-high;
|
||
|
|
};
|
||
|
|
|
||
|
|
memory-controller@7000f400 {
|
||
|
|
emc-table@83250 {
|
||
|
|
reg = <83250>;
|
||
|
|
compatible = "nvidia,tegra20-emc-table";
|
||
|
|
clock-frequency = <83250>;
|
||
|
|
nvidia,emc-registers = <0x00000005 0x00000011
|
||
|
|
0x00000004 0x00000002 0x00000004 0x00000004
|
||
|
|
0x00000001 0x0000000a 0x00000002 0x00000002
|
||
|
|
0x00000001 0x00000001 0x00000003 0x00000004
|
||
|
|
0x00000003 0x00000009 0x0000000c 0x0000025f
|
||
|
|
0x00000000 0x00000003 0x00000003 0x00000002
|
||
|
|
0x00000002 0x00000001 0x00000008 0x000000c8
|
||
|
|
0x00000003 0x00000005 0x00000003 0x0000000c
|
||
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
||
|
|
0x00000000 0x00000000 0x00000083 0x00520006
|
||
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
||
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||
|
|
};
|
||
|
|
emc-table@133200 {
|
||
|
|
reg = <133200>;
|
||
|
|
compatible = "nvidia,tegra20-emc-table";
|
||
|
|
clock-frequency = <133200>;
|
||
|
|
nvidia,emc-registers = <0x00000008 0x00000019
|
||
|
|
0x00000006 0x00000002 0x00000004 0x00000004
|
||
|
|
0x00000001 0x0000000a 0x00000002 0x00000002
|
||
|
|
0x00000002 0x00000001 0x00000003 0x00000004
|
||
|
|
0x00000003 0x00000009 0x0000000c 0x0000039f
|
||
|
|
0x00000000 0x00000003 0x00000003 0x00000002
|
||
|
|
0x00000002 0x00000001 0x00000008 0x000000c8
|
||
|
|
0x00000003 0x00000007 0x00000003 0x0000000c
|
||
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
||
|
|
0x00000000 0x00000000 0x00000083 0x00510006
|
||
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
||
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||
|
|
};
|
||
|
|
emc-table@166500 {
|
||
|
|
reg = <166500>;
|
||
|
|
compatible = "nvidia,tegra20-emc-table";
|
||
|
|
clock-frequency = <166500>;
|
||
|
|
nvidia,emc-registers = <0x0000000a 0x00000021
|
||
|
|
0x00000008 0x00000003 0x00000004 0x00000004
|
||
|
|
0x00000002 0x0000000a 0x00000003 0x00000003
|
||
|
|
0x00000002 0x00000001 0x00000003 0x00000004
|
||
|
|
0x00000003 0x00000009 0x0000000c 0x000004df
|
||
|
|
0x00000000 0x00000003 0x00000003 0x00000003
|
||
|
|
0x00000003 0x00000001 0x00000009 0x000000c8
|
||
|
|
0x00000003 0x00000009 0x00000004 0x0000000c
|
||
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
||
|
|
0x00000000 0x00000000 0x00000083 0x004f0006
|
||
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
||
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||
|
|
};
|
||
|
|
emc-table@333000 {
|
||
|
|
reg = <333000>;
|
||
|
|
compatible = "nvidia,tegra20-emc-table";
|
||
|
|
clock-frequency = <333000>;
|
||
|
|
nvidia,emc-registers = <0x00000014 0x00000041
|
||
|
|
0x0000000f 0x00000005 0x00000004 0x00000005
|
||
|
|
0x00000003 0x0000000a 0x00000005 0x00000005
|
||
|
|
0x00000004 0x00000001 0x00000003 0x00000004
|
||
|
|
0x00000003 0x00000009 0x0000000c 0x000009ff
|
||
|
|
0x00000000 0x00000003 0x00000003 0x00000005
|
||
|
|
0x00000005 0x00000001 0x0000000e 0x000000c8
|
||
|
|
0x00000003 0x00000011 0x00000006 0x0000000c
|
||
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
||
|
|
0x00000000 0x00000000 0x00000083 0x00380006
|
||
|
|
0x00000010 0x00000008 0x00000000 0x00000000
|
||
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usb@c5004000 {
|
||
|
|
status = "okay";
|
||
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
|
||
|
|
GPIO_ACTIVE_LOW>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb-phy@c5004000 {
|
||
|
|
status = "okay";
|
||
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
|
||
|
|
GPIO_ACTIVE_LOW>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhci@c8000600 {
|
||
|
|
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clocks {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
clk32k_in: clock@0 {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
reg = <0>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <32768>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
regulators {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
vdd_3v3_reg: regulator@100 {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
reg = <100>;
|
||
|
|
regulator-name = "vdd_3v3";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-always-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
regulator@101 {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
reg = <101>;
|
||
|
|
regulator-name = "internal_usb";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
enable-active-high;
|
||
|
|
regulator-boot-on;
|
||
|
|
regulator-always-on;
|
||
|
|
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sound {
|
||
|
|
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
|
||
|
|
"nvidia,tegra-audio-wm9712";
|
||
|
|
nvidia,model = "Colibri T20 AC97 Audio";
|
||
|
|
|
||
|
|
nvidia,audio-routing =
|
||
|
|
"Headphone", "HPOUTL",
|
||
|
|
"Headphone", "HPOUTR",
|
||
|
|
"LineIn", "LINEINL",
|
||
|
|
"LineIn", "LINEINR",
|
||
|
|
"Mic", "MIC1";
|
||
|
|
|
||
|
|
nvidia,ac97-controller = <&ac97>;
|
||
|
|
|
||
|
|
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
||
|
|
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
||
|
|
<&tegra_car TEGRA20_CLK_CDEV1>;
|
||
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
||
|
|
};
|
||
|
|
};
|