379 lines
10 KiB
C
379 lines
10 KiB
C
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/*
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* Broadcom Brahma-B15 CPU read-ahead cache management functions
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*
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* Copyright (C) 2015-2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/of_address.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/syscore_ops.h>
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#include <linux/reboot.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-b15-rac.h>
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extern void v7_flush_kern_cache_all(void);
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/* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */
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#define RAC_CONFIG0_REG (0x78)
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#define RACENPREF_MASK (0x3)
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#define RACPREFINST_SHIFT (0)
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#define RACENINST_SHIFT (2)
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#define RACPREFDATA_SHIFT (4)
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#define RACENDATA_SHIFT (6)
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#define RAC_CPU_SHIFT (8)
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#define RACCFG_MASK (0xff)
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#define RAC_CONFIG1_REG (0x7c)
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/* Brahma-B15 is a quad-core only design */
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#define B15_RAC_FLUSH_REG (0x80)
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/* Brahma-B53 is an octo-core design */
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#define B53_RAC_FLUSH_REG (0x84)
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#define FLUSH_RAC (1 << 0)
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/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
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#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
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RACENPREF_MASK << RACENINST_SHIFT | \
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1 << RACPREFDATA_SHIFT | \
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RACENPREF_MASK << RACENDATA_SHIFT)
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#define RAC_ENABLED 0
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/* Special state where we want to bypass the spinlock and call directly
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* into the v7 cache maintenance operations during suspend/resume
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*/
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#define RAC_SUSPENDED 1
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static void __iomem *b15_rac_base;
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static DEFINE_SPINLOCK(rac_lock);
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static u32 rac_config0_reg;
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static u32 rac_flush_offset;
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/* Initialization flag to avoid checking for b15_rac_base, and to prevent
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* multi-platform kernels from crashing here as well.
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*/
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static unsigned long b15_rac_flags;
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static inline u32 __b15_rac_disable(void)
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{
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u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
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__raw_writel(0, b15_rac_base + RAC_CONFIG0_REG);
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dmb();
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return val;
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}
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static inline void __b15_rac_flush(void)
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{
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u32 reg;
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__raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset);
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do {
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/* This dmb() is required to force the Bus Interface Unit
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* to clean oustanding writes, and forces an idle cycle
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* to be inserted.
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*/
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dmb();
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reg = __raw_readl(b15_rac_base + rac_flush_offset);
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} while (reg & FLUSH_RAC);
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}
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static inline u32 b15_rac_disable_and_flush(void)
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{
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u32 reg;
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reg = __b15_rac_disable();
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__b15_rac_flush();
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return reg;
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}
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static inline void __b15_rac_enable(u32 val)
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{
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__raw_writel(val, b15_rac_base + RAC_CONFIG0_REG);
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/* dsb() is required here to be consistent with __flush_icache_all() */
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dsb();
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}
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#define BUILD_RAC_CACHE_OP(name, bar) \
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void b15_flush_##name(void) \
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{ \
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unsigned int do_flush; \
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u32 val = 0; \
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\
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if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \
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v7_flush_##name(); \
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bar; \
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return; \
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} \
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\
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spin_lock(&rac_lock); \
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do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \
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if (do_flush) \
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val = b15_rac_disable_and_flush(); \
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v7_flush_##name(); \
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if (!do_flush) \
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bar; \
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else \
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__b15_rac_enable(val); \
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spin_unlock(&rac_lock); \
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}
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#define nobarrier
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/* The readahead cache present in the Brahma-B15 CPU is a special piece of
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* hardware after the integrated L2 cache of the B15 CPU complex whose purpose
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* is to prefetch instruction and/or data with a line size of either 64 bytes
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* or 256 bytes. The rationale is that the data-bus of the CPU interface is
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* optimized for 256-bytes transactions, and enabling the readahead cache
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* provides a significant performance boost we want it enabled (typically
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* twice the performance for a memcpy benchmark application).
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*
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* The readahead cache is transparent for Modified Virtual Addresses
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* cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
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* DCCIMVAC.
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*
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* It is however not transparent for the following cache maintenance
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* operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely
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* what we are patching here with our BUILD_RAC_CACHE_OP here.
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*/
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BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier);
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static void b15_rac_enable(void)
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{
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unsigned int cpu;
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u32 enable = 0;
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for_each_possible_cpu(cpu)
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enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT));
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b15_rac_disable_and_flush();
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__b15_rac_enable(enable);
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}
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static int b15_rac_reboot_notifier(struct notifier_block *nb,
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unsigned long action,
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void *data)
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{
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/* During kexec, we are not yet migrated on the boot CPU, so we need to
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* make sure we are SMP safe here. Once the RAC is disabled, flag it as
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* suspended such that the hotplug notifier returns early.
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*/
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if (action == SYS_RESTART) {
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spin_lock(&rac_lock);
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b15_rac_disable_and_flush();
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clear_bit(RAC_ENABLED, &b15_rac_flags);
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set_bit(RAC_SUSPENDED, &b15_rac_flags);
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spin_unlock(&rac_lock);
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block b15_rac_reboot_nb = {
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.notifier_call = b15_rac_reboot_notifier,
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};
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/* The CPU hotplug case is the most interesting one, we basically need to make
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* sure that the RAC is disabled for the entire system prior to having a CPU
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* die, in particular prior to this dying CPU having exited the coherency
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* domain.
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*
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* Once this CPU is marked dead, we can safely re-enable the RAC for the
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* remaining CPUs in the system which are still online.
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*
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* Offlining a CPU is the problematic case, onlining a CPU is not much of an
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* issue since the CPU and its cache-level hierarchy will start filling with
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* the RAC disabled, so L1 and L2 only.
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*
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* In this function, we should NOT have to verify any unsafe setting/condition
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* b15_rac_base:
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*
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* It is protected by the RAC_ENABLED flag which is cleared by default, and
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* being cleared when initial procedure is done. b15_rac_base had been set at
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* that time.
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*
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* RAC_ENABLED:
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* There is a small timing windows, in b15_rac_init(), between
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* cpuhp_setup_state_*()
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* ...
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* set RAC_ENABLED
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* However, there is no hotplug activity based on the Linux booting procedure.
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*
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* Since we have to disable RAC for all cores, we keep RAC on as long as as
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* possible (disable it as late as possible) to gain the cache benefit.
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*
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* Thus, dying/dead states are chosen here
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*
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* We are choosing not do disable the RAC on a per-CPU basis, here, if we did
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* we would want to consider disabling it as early as possible to benefit the
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* other active CPUs.
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*/
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/* Running on the dying CPU */
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static int b15_rac_dying_cpu(unsigned int cpu)
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{
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/* During kexec/reboot, the RAC is disabled via the reboot notifier
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* return early here.
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*/
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if (test_bit(RAC_SUSPENDED, &b15_rac_flags))
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return 0;
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spin_lock(&rac_lock);
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/* Indicate that we are starting a hotplug procedure */
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__clear_bit(RAC_ENABLED, &b15_rac_flags);
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/* Disable the readahead cache and save its value to a global */
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rac_config0_reg = b15_rac_disable_and_flush();
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spin_unlock(&rac_lock);
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return 0;
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}
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/* Running on a non-dying CPU */
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static int b15_rac_dead_cpu(unsigned int cpu)
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{
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/* During kexec/reboot, the RAC is disabled via the reboot notifier
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* return early here.
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*/
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if (test_bit(RAC_SUSPENDED, &b15_rac_flags))
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return 0;
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spin_lock(&rac_lock);
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/* And enable it */
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__b15_rac_enable(rac_config0_reg);
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__set_bit(RAC_ENABLED, &b15_rac_flags);
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spin_unlock(&rac_lock);
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return 0;
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}
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static int b15_rac_suspend(void)
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{
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/* Suspend the read-ahead cache oeprations, forcing our cache
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* implementation to fallback to the regular ARMv7 calls.
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*
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* We are guaranteed to be running on the boot CPU at this point and
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* with every other CPU quiesced, so setting RAC_SUSPENDED is not racy
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* here.
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*/
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rac_config0_reg = b15_rac_disable_and_flush();
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set_bit(RAC_SUSPENDED, &b15_rac_flags);
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return 0;
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}
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static void b15_rac_resume(void)
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{
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/* Coming out of a S3 suspend/resume cycle, the read-ahead cache
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* register RAC_CONFIG0_REG will be restored to its default value, make
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* sure we re-enable it and set the enable flag, we are also guaranteed
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* to run on the boot CPU, so not racy again.
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*/
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__b15_rac_enable(rac_config0_reg);
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clear_bit(RAC_SUSPENDED, &b15_rac_flags);
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}
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static struct syscore_ops b15_rac_syscore_ops = {
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.suspend = b15_rac_suspend,
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.resume = b15_rac_resume,
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};
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static int __init b15_rac_init(void)
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{
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struct device_node *dn, *cpu_dn;
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int ret = 0, cpu;
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u32 reg, en_mask = 0;
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dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
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if (!dn)
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return -ENODEV;
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if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
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goto out;
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b15_rac_base = of_iomap(dn, 0);
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if (!b15_rac_base) {
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pr_err("failed to remap BIU control base\n");
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ret = -ENOMEM;
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goto out;
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}
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cpu_dn = of_get_cpu_node(0, NULL);
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if (!cpu_dn) {
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ret = -ENODEV;
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goto out;
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}
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if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
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rac_flush_offset = B15_RAC_FLUSH_REG;
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else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
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rac_flush_offset = B53_RAC_FLUSH_REG;
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else {
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pr_err("Unsupported CPU\n");
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of_node_put(cpu_dn);
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ret = -EINVAL;
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goto out;
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}
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of_node_put(cpu_dn);
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ret = register_reboot_notifier(&b15_rac_reboot_nb);
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if (ret) {
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pr_err("failed to register reboot notifier\n");
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iounmap(b15_rac_base);
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goto out;
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}
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if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
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ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
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"arm/cache-b15-rac:dead",
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NULL, b15_rac_dead_cpu);
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if (ret)
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goto out_unmap;
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ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING,
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"arm/cache-b15-rac:dying",
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NULL, b15_rac_dying_cpu);
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if (ret)
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goto out_cpu_dead;
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}
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if (IS_ENABLED(CONFIG_PM_SLEEP))
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register_syscore_ops(&b15_rac_syscore_ops);
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spin_lock(&rac_lock);
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reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
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for_each_possible_cpu(cpu)
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en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT));
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WARN(reg & en_mask, "Read-ahead cache not previously disabled\n");
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b15_rac_enable();
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set_bit(RAC_ENABLED, &b15_rac_flags);
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|
|
spin_unlock(&rac_lock);
|
||
|
|
|
||
|
|
pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n",
|
||
|
|
b15_rac_base + RAC_CONFIG0_REG);
|
||
|
|
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
out_cpu_dead:
|
||
|
|
cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING);
|
||
|
|
out_unmap:
|
||
|
|
unregister_reboot_notifier(&b15_rac_reboot_nb);
|
||
|
|
iounmap(b15_rac_base);
|
||
|
|
out:
|
||
|
|
of_node_put(dn);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
arch_initcall(b15_rac_init);
|