482 lines
13 KiB
C
482 lines
13 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
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*
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* Routines for PCI DMA mapping. See Documentation/DMA-API.txt for
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* a description of how these routines should be used.
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*/
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#include <linux/gfp.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <asm/dma.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/sn_sal.h>
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#define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
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#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
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/**
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* sn_dma_supported - test a DMA mask
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* @dev: device to test
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* @mask: DMA mask to test
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*
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* Return whether the given PCI device DMA address mask can be supported
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* properly. For example, if your device can only drive the low 24-bits
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* during PCI bus mastering, then you would pass 0x00ffffff as the mask to
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* this function. Of course, SN only supports devices that have 32 or more
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* address bits when using the PMU.
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*/
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static int sn_dma_supported(struct device *dev, u64 mask)
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{
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BUG_ON(!dev_is_pci(dev));
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if (mask < 0x7fffffff)
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return 0;
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return 1;
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}
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/**
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* sn_dma_set_mask - set the DMA mask
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* @dev: device to set
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* @dma_mask: new mask
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*
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* Set @dev's DMA mask if the hw supports it.
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*/
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int sn_dma_set_mask(struct device *dev, u64 dma_mask)
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{
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BUG_ON(!dev_is_pci(dev));
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if (!sn_dma_supported(dev, dma_mask))
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return 0;
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*dev->dma_mask = dma_mask;
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return 1;
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}
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EXPORT_SYMBOL(sn_dma_set_mask);
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/**
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* sn_dma_alloc_coherent - allocate memory for coherent DMA
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* @dev: device to allocate for
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* @size: size of the region
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* @dma_handle: DMA (bus) address
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* @flags: memory allocation flags
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*
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* dma_alloc_coherent() returns a pointer to a memory region suitable for
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* coherent DMA traffic to/from a PCI device. On SN platforms, this means
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* that @dma_handle will have the %PCIIO_DMA_CMD flag set.
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*
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* This interface is usually used for "command" streams (e.g. the command
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* queue for a SCSI controller). See Documentation/DMA-API.txt for
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* more information.
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*/
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static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t * dma_handle, gfp_t flags,
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unsigned long attrs)
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{
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void *cpuaddr;
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unsigned long phys_addr;
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int node;
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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BUG_ON(!dev_is_pci(dev));
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/*
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* Allocate the memory.
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*/
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node = pcibus_to_node(pdev->bus);
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if (likely(node >=0)) {
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struct page *p = __alloc_pages_node(node,
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flags, get_order(size));
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if (likely(p))
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cpuaddr = page_address(p);
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else
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return NULL;
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} else
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cpuaddr = (void *)__get_free_pages(flags, get_order(size));
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if (unlikely(!cpuaddr))
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return NULL;
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memset(cpuaddr, 0x0, size);
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/* physical addr. of the memory we just got */
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phys_addr = __pa(cpuaddr);
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/*
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* 64 bit address translations should never fail.
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* 32 bit translations can fail if there are insufficient mapping
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* resources.
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*/
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*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
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SN_DMA_ADDR_PHYS);
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if (!*dma_handle) {
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printk(KERN_ERR "%s: out of ATEs\n", __func__);
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free_pages((unsigned long)cpuaddr, get_order(size));
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return NULL;
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}
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return cpuaddr;
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}
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/**
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* sn_pci_free_coherent - free memory associated with coherent DMAable region
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* @dev: device to free for
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* @size: size to free
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* @cpu_addr: kernel virtual address to free
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* @dma_handle: DMA address associated with this region
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*
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* Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
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* any associated IOMMU mappings.
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*/
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static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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BUG_ON(!dev_is_pci(dev));
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provider->dma_unmap(pdev, dma_handle, 0);
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free_pages((unsigned long)cpu_addr, get_order(size));
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}
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/**
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* sn_dma_map_single_attrs - map a single page for DMA
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* @dev: device to map for
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* @cpu_addr: kernel virtual address of the region to map
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* @size: size of the region
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* @direction: DMA direction
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* @attrs: optional dma attributes
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*
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* Map the region pointed to by @cpu_addr for DMA and return the
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* DMA address.
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*
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* We map this to the one step pcibr_dmamap_trans interface rather than
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* the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
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* no way of saving the dmamap handle from the alloc to later free
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* (which is pretty much unacceptable).
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*
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* mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
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* dma_map_consistent() so that writes force a flush of pending DMA.
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* (See "SGI Altix Architecture Considerations for Linux Device Drivers",
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* Document Number: 007-4763-001)
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*
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* TODO: simplify our interface;
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* figure out how to save dmamap handle so can use two step.
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*/
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static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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void *cpu_addr = page_address(page) + offset;
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dma_addr_t dma_addr;
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unsigned long phys_addr;
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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BUG_ON(!dev_is_pci(dev));
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phys_addr = __pa(cpu_addr);
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if (attrs & DMA_ATTR_WRITE_BARRIER)
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dma_addr = provider->dma_map_consistent(pdev, phys_addr,
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size, SN_DMA_ADDR_PHYS);
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else
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dma_addr = provider->dma_map(pdev, phys_addr, size,
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SN_DMA_ADDR_PHYS);
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if (!dma_addr) {
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printk(KERN_ERR "%s: out of ATEs\n", __func__);
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return 0;
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}
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return dma_addr;
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}
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/**
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* sn_dma_unmap_single_attrs - unamp a DMA mapped page
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* @dev: device to sync
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* @dma_addr: DMA address to sync
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* @size: size of region
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* @direction: DMA direction
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* @attrs: optional dma attributes
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*
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* This routine is supposed to sync the DMA region specified
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* by @dma_handle into the coherence domain. On SN, we're always cache
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* coherent, so we just need to free any ATEs associated with this mapping.
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*/
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static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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BUG_ON(!dev_is_pci(dev));
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provider->dma_unmap(pdev, dma_addr, dir);
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}
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/**
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* sn_dma_unmap_sg - unmap a DMA scatterlist
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* @dev: device to unmap
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* @sg: scatterlist to unmap
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* @nhwentries: number of scatterlist entries
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* @direction: DMA direction
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* @attrs: optional dma attributes
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*
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* Unmap a set of streaming mode DMA translations.
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*/
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static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nhwentries, enum dma_data_direction dir,
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unsigned long attrs)
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{
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int i;
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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struct scatterlist *sg;
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BUG_ON(!dev_is_pci(dev));
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for_each_sg(sgl, sg, nhwentries, i) {
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provider->dma_unmap(pdev, sg->dma_address, dir);
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sg->dma_address = (dma_addr_t) NULL;
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sg->dma_length = 0;
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}
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}
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/**
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* sn_dma_map_sg - map a scatterlist for DMA
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* @dev: device to map for
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* @sg: scatterlist to map
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* @nhwentries: number of entries
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* @direction: direction of the DMA transaction
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* @attrs: optional dma attributes
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*
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* mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
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* dma_map_consistent() so that writes force a flush of pending DMA.
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* (See "SGI Altix Architecture Considerations for Linux Device Drivers",
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* Document Number: 007-4763-001)
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*
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* Maps each entry of @sg for DMA.
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*/
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static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
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int nhwentries, enum dma_data_direction dir,
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unsigned long attrs)
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{
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unsigned long phys_addr;
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struct scatterlist *saved_sg = sgl, *sg;
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struct pci_dev *pdev = to_pci_dev(dev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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int i;
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BUG_ON(!dev_is_pci(dev));
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/*
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* Setup a DMA address for each entry in the scatterlist.
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*/
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for_each_sg(sgl, sg, nhwentries, i) {
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dma_addr_t dma_addr;
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phys_addr = SG_ENT_PHYS_ADDRESS(sg);
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if (attrs & DMA_ATTR_WRITE_BARRIER)
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dma_addr = provider->dma_map_consistent(pdev,
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phys_addr,
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sg->length,
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SN_DMA_ADDR_PHYS);
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else
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dma_addr = provider->dma_map(pdev, phys_addr,
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sg->length,
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SN_DMA_ADDR_PHYS);
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sg->dma_address = dma_addr;
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if (!sg->dma_address) {
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printk(KERN_ERR "%s: out of ATEs\n", __func__);
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/*
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* Free any successfully allocated entries.
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*/
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if (i > 0)
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sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
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return 0;
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}
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sg->dma_length = sg->length;
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}
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return nhwentries;
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}
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static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return 0;
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}
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u64 sn_dma_get_required_mask(struct device *dev)
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{
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return DMA_BIT_MASK(64);
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}
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EXPORT_SYMBOL_GPL(sn_dma_get_required_mask);
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char *sn_pci_get_legacy_mem(struct pci_bus *bus)
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{
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if (!SN_PCIBUS_BUSSOFT(bus))
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return ERR_PTR(-ENODEV);
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return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
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}
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int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
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{
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unsigned long addr;
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int ret;
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struct ia64_sal_retval isrv;
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/*
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* First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
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|
|
* around hw issues at the pci bus level. SGI proms older than
|
||
|
|
* 4.10 don't implement this.
|
||
|
|
*/
|
||
|
|
|
||
|
|
SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
|
||
|
|
pci_domain_nr(bus), bus->number,
|
||
|
|
0, /* io */
|
||
|
|
0, /* read */
|
||
|
|
port, size, __pa(val));
|
||
|
|
|
||
|
|
if (isrv.status == 0)
|
||
|
|
return size;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If the above failed, retry using the SAL_PROBE call which should
|
||
|
|
* be present in all proms (but which cannot work round PCI chipset
|
||
|
|
* bugs). This code is retained for compatibility with old
|
||
|
|
* pre-4.10 proms, and should be removed at some point in the future.
|
||
|
|
*/
|
||
|
|
|
||
|
|
if (!SN_PCIBUS_BUSSOFT(bus))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
|
||
|
|
addr += port;
|
||
|
|
|
||
|
|
ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
|
||
|
|
|
||
|
|
if (ret == 2)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (ret == 1)
|
||
|
|
*val = -1;
|
||
|
|
|
||
|
|
return size;
|
||
|
|
}
|
||
|
|
|
||
|
|
int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
|
||
|
|
{
|
||
|
|
int ret = size;
|
||
|
|
unsigned long paddr;
|
||
|
|
unsigned long *addr;
|
||
|
|
struct ia64_sal_retval isrv;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
|
||
|
|
* around hw issues at the pci bus level. SGI proms older than
|
||
|
|
* 4.10 don't implement this.
|
||
|
|
*/
|
||
|
|
|
||
|
|
SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
|
||
|
|
pci_domain_nr(bus), bus->number,
|
||
|
|
0, /* io */
|
||
|
|
1, /* write */
|
||
|
|
port, size, __pa(&val));
|
||
|
|
|
||
|
|
if (isrv.status == 0)
|
||
|
|
return size;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If the above failed, retry using the SAL_PROBE call which should
|
||
|
|
* be present in all proms (but which cannot work round PCI chipset
|
||
|
|
* bugs). This code is retained for compatibility with old
|
||
|
|
* pre-4.10 proms, and should be removed at some point in the future.
|
||
|
|
*/
|
||
|
|
|
||
|
|
if (!SN_PCIBUS_BUSSOFT(bus)) {
|
||
|
|
ret = -ENODEV;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Put the phys addr in uncached space */
|
||
|
|
paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
|
||
|
|
paddr += port;
|
||
|
|
addr = (unsigned long *)paddr;
|
||
|
|
|
||
|
|
switch (size) {
|
||
|
|
case 1:
|
||
|
|
*(volatile u8 *)(addr) = (u8)(val);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
*(volatile u16 *)(addr) = (u16)(val);
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
*(volatile u32 *)(addr) = (u32)(val);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
ret = -EINVAL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
out:
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct dma_map_ops sn_dma_ops = {
|
||
|
|
.alloc = sn_dma_alloc_coherent,
|
||
|
|
.free = sn_dma_free_coherent,
|
||
|
|
.map_page = sn_dma_map_page,
|
||
|
|
.unmap_page = sn_dma_unmap_page,
|
||
|
|
.map_sg = sn_dma_map_sg,
|
||
|
|
.unmap_sg = sn_dma_unmap_sg,
|
||
|
|
.sync_single_for_cpu = sn_dma_sync_single_for_cpu,
|
||
|
|
.sync_sg_for_cpu = sn_dma_sync_sg_for_cpu,
|
||
|
|
.sync_single_for_device = sn_dma_sync_single_for_device,
|
||
|
|
.sync_sg_for_device = sn_dma_sync_sg_for_device,
|
||
|
|
.mapping_error = sn_dma_mapping_error,
|
||
|
|
.dma_supported = sn_dma_supported,
|
||
|
|
};
|
||
|
|
|
||
|
|
void sn_dma_init(void)
|
||
|
|
{
|
||
|
|
dma_ops = &sn_dma_ops;
|
||
|
|
}
|