274 lines
6.3 KiB
C
274 lines
6.3 KiB
C
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/*
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* Atheros AR71XX/AR724X specific PCI setup code
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/resource.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/irq.h>
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#include "pci.h"
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static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
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static const struct ath79_pci_irq *ath79_pci_irq_map;
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static unsigned ath79_pci_nr_irqs;
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static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
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{
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.slot = 17,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(0),
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}, {
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.slot = 18,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(1),
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}, {
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.slot = 19,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(2),
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}
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};
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static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
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{
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.slot = 0,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(0),
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}
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};
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static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
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{
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.bus = 0,
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.slot = 0,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(0),
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},
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{
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.bus = 1,
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.slot = 0,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(1),
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},
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};
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int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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{
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int irq = -1;
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int i;
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if (ath79_pci_nr_irqs == 0 ||
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ath79_pci_irq_map == NULL) {
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if (soc_is_ar71xx()) {
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ath79_pci_irq_map = ar71xx_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
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} else if (soc_is_ar724x() ||
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soc_is_ar9342() ||
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soc_is_ar9344()) {
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ath79_pci_irq_map = ar724x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
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} else if (soc_is_qca955x()) {
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ath79_pci_irq_map = qca955x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
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} else {
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pr_crit("pci %s: invalid irq map\n",
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pci_name((struct pci_dev *) dev));
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return irq;
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}
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}
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for (i = 0; i < ath79_pci_nr_irqs; i++) {
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const struct ath79_pci_irq *entry;
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entry = &ath79_pci_irq_map[i];
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if (entry->bus == dev->bus->number &&
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entry->slot == slot &&
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entry->pin == pin) {
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irq = entry->irq;
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break;
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}
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}
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if (irq < 0)
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pr_crit("pci %s: no irq found for pin %u\n",
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pci_name((struct pci_dev *) dev), pin);
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else
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pr_info("pci %s: using irq %d for pin %u\n",
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pci_name((struct pci_dev *) dev), irq, pin);
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return irq;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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if (ath79_pci_plat_dev_init)
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return ath79_pci_plat_dev_init(dev);
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return 0;
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}
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void __init ath79_pci_set_irq_map(unsigned nr_irqs,
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const struct ath79_pci_irq *map)
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{
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ath79_pci_nr_irqs = nr_irqs;
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ath79_pci_irq_map = map;
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}
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void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
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{
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ath79_pci_plat_dev_init = func;
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}
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static struct platform_device *
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ath79_register_pci_ar71xx(void)
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{
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struct platform_device *pdev;
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struct resource res[4];
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memset(res, 0, sizeof(res));
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res[0].name = "cfg_base";
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res[0].flags = IORESOURCE_MEM;
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res[0].start = AR71XX_PCI_CFG_BASE;
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res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
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res[1].flags = IORESOURCE_IRQ;
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res[1].start = ATH79_CPU_IRQ(2);
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res[1].end = ATH79_CPU_IRQ(2);
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res[2].name = "io_base";
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res[2].flags = IORESOURCE_IO;
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res[2].start = 0;
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res[2].end = 0;
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res[3].name = "mem_base";
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res[3].flags = IORESOURCE_MEM;
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res[3].start = AR71XX_PCI_MEM_BASE;
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res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
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pdev = platform_device_register_simple("ar71xx-pci", -1,
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res, ARRAY_SIZE(res));
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return pdev;
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}
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static struct platform_device *
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ath79_register_pci_ar724x(int id,
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unsigned long cfg_base,
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unsigned long ctrl_base,
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unsigned long crp_base,
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unsigned long mem_base,
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unsigned long mem_size,
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unsigned long io_base,
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int irq)
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{
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struct platform_device *pdev;
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struct resource res[6];
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memset(res, 0, sizeof(res));
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res[0].name = "cfg_base";
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res[0].flags = IORESOURCE_MEM;
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res[0].start = cfg_base;
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res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
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res[1].name = "ctrl_base";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = ctrl_base;
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res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
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res[2].flags = IORESOURCE_IRQ;
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res[2].start = irq;
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res[2].end = irq;
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res[3].name = "mem_base";
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res[3].flags = IORESOURCE_MEM;
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res[3].start = mem_base;
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res[3].end = mem_base + mem_size - 1;
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res[4].name = "io_base";
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res[4].flags = IORESOURCE_IO;
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res[4].start = io_base;
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res[4].end = io_base;
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res[5].name = "crp_base";
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res[5].flags = IORESOURCE_MEM;
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res[5].start = crp_base;
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res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
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pdev = platform_device_register_simple("ar724x-pci", id,
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res, ARRAY_SIZE(res));
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return pdev;
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}
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int __init ath79_register_pci(void)
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{
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struct platform_device *pdev = NULL;
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if (soc_is_ar71xx()) {
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pdev = ath79_register_pci_ar71xx();
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} else if (soc_is_ar724x()) {
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pdev = ath79_register_pci_ar724x(-1,
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AR724X_PCI_CFG_BASE,
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AR724X_PCI_CTRL_BASE,
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AR724X_PCI_CRP_BASE,
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AR724X_PCI_MEM_BASE,
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AR724X_PCI_MEM_SIZE,
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0,
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ATH79_CPU_IRQ(2));
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} else if (soc_is_ar9342() ||
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soc_is_ar9344()) {
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u32 bootstrap;
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
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return -ENODEV;
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pdev = ath79_register_pci_ar724x(-1,
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AR724X_PCI_CFG_BASE,
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AR724X_PCI_CTRL_BASE,
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AR724X_PCI_CRP_BASE,
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AR724X_PCI_MEM_BASE,
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AR724X_PCI_MEM_SIZE,
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0,
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ATH79_IP2_IRQ(0));
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} else if (soc_is_qca9558()) {
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pdev = ath79_register_pci_ar724x(0,
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QCA955X_PCI_CFG_BASE0,
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QCA955X_PCI_CTRL_BASE0,
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QCA955X_PCI_CRP_BASE0,
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QCA955X_PCI_MEM_BASE0,
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QCA955X_PCI_MEM_SIZE,
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0,
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ATH79_IP2_IRQ(0));
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pdev = ath79_register_pci_ar724x(1,
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QCA955X_PCI_CFG_BASE1,
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QCA955X_PCI_CTRL_BASE1,
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QCA955X_PCI_CRP_BASE1,
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QCA955X_PCI_MEM_BASE1,
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QCA955X_PCI_MEM_SIZE,
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1,
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ATH79_IP3_IRQ(2));
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} else {
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/* No PCI support */
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return -ENODEV;
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}
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if (!pdev)
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pr_err("unable to register PCI controller device\n");
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return pdev ? 0 : -ENODEV;
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}
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