361 lines
12 KiB
C
361 lines
12 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Functions for XAUI initialization, configuration,
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* and monitoring.
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*
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-config.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-pko-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-pcsx-defs.h>
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#include <asm/octeon/cvmx-pcsxx-defs.h>
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int __cvmx_helper_xaui_enumerate(int interface)
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{
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union cvmx_gmxx_hg2_control gmx_hg2_control;
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/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
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gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
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if (gmx_hg2_control.s.hg2tx_en)
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return 16;
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else
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return 1;
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}
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/**
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* Probe a XAUI interface and determine the number of ports
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* connected to it. The XAUI interface should still be down
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* after this call.
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*
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* @interface: Interface to probe
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*
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* Returns Number of ports on the interface. Zero to disable.
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*/
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int __cvmx_helper_xaui_probe(int interface)
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{
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int i;
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union cvmx_gmxx_inf_mode mode;
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/*
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* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
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* interface needs to be enabled before IPD otherwise per port
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* backpressure may not work properly.
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*/
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mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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mode.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
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__cvmx_helper_setup_gmx(interface, 1);
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/*
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* Setup PKO to support 16 ports for HiGig2 virtual
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* ports. We're pointing all of the PKO packet ports for this
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* interface to the XAUI. This allows us to use HiGig2
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* backpressure per port.
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*/
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for (i = 0; i < 16; i++) {
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union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
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pko_mem_port_ptrs.u64 = 0;
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/*
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* We set each PKO port to have equal priority in a
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* round robin fashion.
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*/
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pko_mem_port_ptrs.s.static_p = 0;
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pko_mem_port_ptrs.s.qos_mask = 0xff;
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/* All PKO ports map to the same XAUI hardware port */
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pko_mem_port_ptrs.s.eid = interface * 4;
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pko_mem_port_ptrs.s.pid = interface * 16 + i;
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cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
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}
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return __cvmx_helper_xaui_enumerate(interface);
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}
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/**
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* Bringup and enable a XAUI interface. After this call packet
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* I/O should be fully functional. This is called with IPD
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* enabled but PKO disabled.
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*
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* @interface: Interface to bring up
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*
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* Returns Zero on success, negative on failure
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*/
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int __cvmx_helper_xaui_enable(int interface)
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{
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union cvmx_gmxx_prtx_cfg gmx_cfg;
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union cvmx_pcsxx_control1_reg xauiCtl;
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union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
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union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
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union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
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union cvmx_gmxx_tx_int_en gmx_tx_int_en;
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union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
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/* Setup PKND */
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if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
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gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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}
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/* (1) Interface has already been enabled. */
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/* (2) Disable GMX. */
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xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
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xauiMiscCtl.s.gmxeno = 1;
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cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
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/* (3) Disable GMX and PCSX interrupts. */
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gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
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gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
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cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
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pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
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cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
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/* (4) Bring up the PCSX and GMX reconciliation layer. */
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/* (4)a Set polarity and lane swapping. */
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/* (4)b */
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gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
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/* Enable better IFG packing and improves performance */
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gmxXauiTxCtl.s.dic_en = 1;
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gmxXauiTxCtl.s.uni_en = 0;
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cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
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/* (4)c Aply reset sequence */
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xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
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xauiCtl.s.lo_pwr = 0;
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/* Issuing a reset here seems to hang some CN68XX chips. */
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if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
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!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
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xauiCtl.s.reset = 1;
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cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
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/* Wait for PCS to come out of reset */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
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reset, ==, 0, 10000))
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return -1;
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/* Wait for PCS to be aligned */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_PCSXX_10GBX_STATUS_REG(interface),
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union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
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return -1;
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/* Wait for RX to be ready */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
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status, ==, 0, 10000))
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return -1;
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/* (6) Configure GMX */
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gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.en = 0;
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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/* Wait for GMX RX to be idle */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
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rx_idle, ==, 1, 10000))
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return -1;
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/* Wait for GMX TX to be idle */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
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tx_idle, ==, 1, 10000))
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return -1;
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/* GMX configure */
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gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.speed = 1;
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gmx_cfg.s.speed_msb = 0;
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gmx_cfg.s.slottime = 1;
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cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
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cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
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cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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/* (7) Clear out any error state */
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cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
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cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
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cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
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cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
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cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
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cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
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/* Wait for receive link */
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
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rcv_lnk, ==, 1, 10000))
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return -1;
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
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xmtflt, ==, 0, 10000))
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return -1;
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if (CVMX_WAIT_FOR_FIELD64
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(CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
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rcvflt, ==, 0, 10000))
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return -1;
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
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cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
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cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
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/* (8) Enable packet reception */
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xauiMiscCtl.s.gmxeno = 0;
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cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
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gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
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__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
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__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
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__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
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__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
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__cvmx_interrupt_gmxx_enable(interface);
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return 0;
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}
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/**
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* Return the link state of an IPD/PKO port as returned by
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* auto negotiation. The result of this function may not match
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* Octeon's link config if auto negotiation has changed since
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* the last call to cvmx_helper_link_set().
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*
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* @ipd_port: IPD/PKO port to query
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*
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* Returns Link state
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*/
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cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
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{
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int interface = cvmx_helper_get_interface_num(ipd_port);
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union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
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union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
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union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
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cvmx_helper_link_info_t result;
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gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
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gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
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pcsxx_status1_reg.u64 =
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cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
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result.u64 = 0;
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/* Only return a link if both RX and TX are happy */
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if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
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(pcsxx_status1_reg.s.rcv_lnk == 1)) {
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 10000;
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} else {
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/* Disable GMX and PCSX interrupts. */
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
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cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
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cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
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}
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return result;
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}
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/**
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* Configure an IPD/PKO port for the specified link state. This
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* function does not influence auto negotiation at the PHY level.
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* The passed link state must always match the link state returned
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* by cvmx_helper_link_get().
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*
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* @ipd_port: IPD/PKO port to configure
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* @link_info: The new link state
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*
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* Returns Zero on success, negative on failure
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*/
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int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
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{
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int interface = cvmx_helper_get_interface_num(ipd_port);
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union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
|
||
|
|
union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
|
||
|
|
|
||
|
|
gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
|
||
|
|
gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
|
||
|
|
|
||
|
|
/* If the link shouldn't be up, then just return */
|
||
|
|
if (!link_info.s.link_up)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/* Do nothing if both RX and TX are happy */
|
||
|
|
if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/* Bring the link up */
|
||
|
|
return __cvmx_helper_xaui_enable(interface);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Configure a port for internal and/or external loopback. Internal loopback
|
||
|
|
* causes packets sent by the port to be received by Octeon. External loopback
|
||
|
|
* causes packets received from the wire to sent out again.
|
||
|
|
*
|
||
|
|
* @ipd_port: IPD/PKO port to loopback.
|
||
|
|
* @enable_internal:
|
||
|
|
* Non zero if you want internal loopback
|
||
|
|
* @enable_external:
|
||
|
|
* Non zero if you want external loopback
|
||
|
|
*
|
||
|
|
* Returns Zero on success, negative on failure.
|
||
|
|
*/
|
||
|
|
extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
|
||
|
|
int enable_internal,
|
||
|
|
int enable_external)
|
||
|
|
{
|
||
|
|
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||
|
|
union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
|
||
|
|
union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
|
||
|
|
|
||
|
|
/* Set the internal loop */
|
||
|
|
pcsxx_control1_reg.u64 =
|
||
|
|
cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
|
||
|
|
pcsxx_control1_reg.s.loopbck1 = enable_internal;
|
||
|
|
cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
|
||
|
|
pcsxx_control1_reg.u64);
|
||
|
|
|
||
|
|
/* Set the external loop */
|
||
|
|
gmxx_xaui_ext_loopback.u64 =
|
||
|
|
cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
|
||
|
|
gmxx_xaui_ext_loopback.s.en = enable_external;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
|
||
|
|
gmxx_xaui_ext_loopback.u64);
|
||
|
|
|
||
|
|
/* Take the link through a reset */
|
||
|
|
return __cvmx_helper_xaui_enable(interface);
|
||
|
|
}
|