379 lines
9.6 KiB
C
379 lines
9.6 KiB
C
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/*
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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* using the CPU's debug registers. Derived from
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* "arch/x86/kernel/hw_breakpoint.c"
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2010 IBM Corporation
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* Author: K.Prasad <prasad@linux.vnet.ibm.com>
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*
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*/
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#include <linux/hw_breakpoint.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/percpu.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/processor.h>
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#include <asm/sstep.h>
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#include <asm/debug.h>
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#include <linux/uaccess.h>
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/*
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* Stores the breakpoints currently in use on each breakpoint address
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* register for every cpu
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*/
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
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/*
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* Returns total number of data or instruction breakpoints available.
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*/
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int hw_breakpoint_slots(int type)
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{
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if (type == TYPE_DATA)
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return HBP_NUM;
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return 0; /* no instruction breakpoints available */
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}
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/*
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* Install a perf counter breakpoint.
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*
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* We seek a free debug address register and use it for this
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* breakpoint.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg);
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*slot = bp;
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/*
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* Do not install DABR values if the instruction must be single-stepped.
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* If so, DABR will be populated in single_step_dabr_instruction().
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*/
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if (current->thread.last_hit_ubp != bp)
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__set_breakpoint(info);
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return 0;
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}
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/*
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* Uninstall the breakpoint contained in the given counter.
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*
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* First we search the debug address register it uses and then we disable
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* it.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg);
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if (*slot != bp) {
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WARN_ONCE(1, "Can't find the breakpoint");
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return;
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}
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*slot = NULL;
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hw_breakpoint_disable();
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}
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/*
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* Perform cleanup of arch-specific counters during unregistration
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* of the perf-event
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*/
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void arch_unregister_hw_breakpoint(struct perf_event *bp)
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{
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/*
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* If the breakpoint is unregistered between a hw_breakpoint_handler()
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* and the single_step_dabr_instruction(), then cleanup the breakpoint
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* restoration variables to prevent dangling pointers.
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* FIXME, this should not be using bp->ctx at all! Sayeth peterz.
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*/
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if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L))
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bp->ctx->task->thread.last_hit_ubp = NULL;
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}
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/*
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* Check for virtual address in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
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{
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return is_kernel_addr(hw->address);
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}
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int arch_bp_generic_fields(int type, int *gen_bp_type)
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{
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*gen_bp_type = 0;
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if (type & HW_BRK_TYPE_READ)
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*gen_bp_type |= HW_BREAKPOINT_R;
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if (type & HW_BRK_TYPE_WRITE)
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*gen_bp_type |= HW_BREAKPOINT_W;
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if (*gen_bp_type == 0)
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return -EINVAL;
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings
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*/
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int hw_breakpoint_arch_parse(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw)
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{
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int ret = -EINVAL, length_max;
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if (!bp)
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return ret;
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hw->type = HW_BRK_TYPE_TRANSLATE;
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if (attr->bp_type & HW_BREAKPOINT_R)
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hw->type |= HW_BRK_TYPE_READ;
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if (attr->bp_type & HW_BREAKPOINT_W)
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hw->type |= HW_BRK_TYPE_WRITE;
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if (hw->type == HW_BRK_TYPE_TRANSLATE)
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/* must set alteast read or write */
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return ret;
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if (!attr->exclude_user)
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hw->type |= HW_BRK_TYPE_USER;
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if (!attr->exclude_kernel)
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hw->type |= HW_BRK_TYPE_KERNEL;
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if (!attr->exclude_hv)
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hw->type |= HW_BRK_TYPE_HYP;
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hw->address = attr->bp_addr;
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hw->len = attr->bp_len;
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/*
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* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
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* and breakpoint addresses are aligned to nearest double-word
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* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
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* 'symbolsize' should satisfy the check below.
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*/
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if (!ppc_breakpoint_available())
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return -ENODEV;
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length_max = 8; /* DABR */
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if (cpu_has_feature(CPU_FTR_DAWR)) {
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length_max = 512 ; /* 64 doublewords */
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/* DAWR region can't cross 512 boundary */
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if ((attr->bp_addr >> 9) !=
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((attr->bp_addr + attr->bp_len - 1) >> 9))
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return -EINVAL;
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}
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if (hw->len >
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(length_max - (hw->address & HW_BREAKPOINT_ALIGN)))
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return -EINVAL;
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return 0;
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}
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/*
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* Restores the breakpoint on the debug registers.
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* Invoke this function if it is known that the execution context is
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* about to change to cause loss of MSR_SE settings.
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*/
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void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
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{
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struct arch_hw_breakpoint *info;
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if (likely(!tsk->thread.last_hit_ubp))
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return;
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info = counter_arch_bp(tsk->thread.last_hit_ubp);
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regs->msr &= ~MSR_SE;
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__set_breakpoint(info);
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tsk->thread.last_hit_ubp = NULL;
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}
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/*
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* Handle debug exception notifications.
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*/
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int hw_breakpoint_handler(struct die_args *args)
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{
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int rc = NOTIFY_STOP;
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struct perf_event *bp;
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struct pt_regs *regs = args->regs;
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#ifndef CONFIG_PPC_8xx
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int stepped = 1;
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unsigned int instr;
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#endif
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struct arch_hw_breakpoint *info;
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unsigned long dar = regs->dar;
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/* Disable breakpoints during exception handling */
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hw_breakpoint_disable();
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/*
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* The counter may be concurrently released but that can only
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* occur from a call_rcu() path. We can then safely fetch
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* the breakpoint, use its callback, touch its counter
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* while we are in an rcu_read_lock() path.
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*/
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rcu_read_lock();
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bp = __this_cpu_read(bp_per_reg);
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if (!bp) {
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rc = NOTIFY_DONE;
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goto out;
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}
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info = counter_arch_bp(bp);
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/*
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* Return early after invoking user-callback function without restoring
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* DABR if the breakpoint is from ptrace which always operates in
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* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
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* generated in do_dabr().
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*/
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if (bp->overflow_handler == ptrace_triggered) {
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perf_bp_event(bp, regs);
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rc = NOTIFY_DONE;
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goto out;
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}
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/*
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* Verify if dar lies within the address range occupied by the symbol
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* being watched to filter extraneous exceptions. If it doesn't,
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* we still need to single-step the instruction, but we don't
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* generate an event.
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*/
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info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
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if (!((bp->attr.bp_addr <= dar) &&
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(dar - bp->attr.bp_addr < bp->attr.bp_len)))
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info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
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#ifndef CONFIG_PPC_8xx
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/* Do not emulate user-space instructions, instead single-step them */
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if (user_mode(regs)) {
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current->thread.last_hit_ubp = bp;
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regs->msr |= MSR_SE;
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goto out;
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}
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stepped = 0;
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instr = 0;
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if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
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stepped = emulate_step(regs, instr);
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/*
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* emulate_step() could not execute it. We've failed in reliably
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* handling the hw-breakpoint. Unregister it and throw a warning
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* message to let the user know about it.
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*/
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if (!stepped) {
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WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
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"0x%lx will be disabled.", info->address);
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perf_event_disable_inatomic(bp);
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goto out;
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}
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#endif
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/*
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* As a policy, the callback is invoked in a 'trigger-after-execute'
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* fashion
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*/
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if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
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perf_bp_event(bp, regs);
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__set_breakpoint(info);
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out:
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rcu_read_unlock();
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return rc;
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}
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NOKPROBE_SYMBOL(hw_breakpoint_handler);
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/*
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* Handle single-step exceptions following a DABR hit.
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*/
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static int single_step_dabr_instruction(struct die_args *args)
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{
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struct pt_regs *regs = args->regs;
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struct perf_event *bp = NULL;
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struct arch_hw_breakpoint *info;
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bp = current->thread.last_hit_ubp;
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/*
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* Check if we are single-stepping as a result of a
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* previous HW Breakpoint exception
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*/
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if (!bp)
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return NOTIFY_DONE;
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info = counter_arch_bp(bp);
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/*
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* We shall invoke the user-defined callback function in the single
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* stepping handler to confirm to 'trigger-after-execute' semantics
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*/
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if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
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perf_bp_event(bp, regs);
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__set_breakpoint(info);
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current->thread.last_hit_ubp = NULL;
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/*
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* If the process was being single-stepped by ptrace, let the
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* other single-step actions occur (e.g. generate SIGTRAP).
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*/
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if (test_thread_flag(TIF_SINGLESTEP))
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return NOTIFY_DONE;
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return NOTIFY_STOP;
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}
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NOKPROBE_SYMBOL(single_step_dabr_instruction);
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/*
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* Handle debug exception notifications.
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*/
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int hw_breakpoint_exceptions_notify(
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struct notifier_block *unused, unsigned long val, void *data)
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{
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int ret = NOTIFY_DONE;
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switch (val) {
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case DIE_DABR_MATCH:
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ret = hw_breakpoint_handler(data);
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break;
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case DIE_SSTEP:
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ret = single_step_dabr_instruction(data);
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break;
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}
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return ret;
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}
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NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify);
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/*
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* Release the user breakpoints used by ptrace
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*/
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void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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struct thread_struct *t = &tsk->thread;
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unregister_hw_breakpoint(t->ptrace_bps[0]);
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t->ptrace_bps[0] = NULL;
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}
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void hw_breakpoint_pmu_read(struct perf_event *bp)
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{
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/* TODO */
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}
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