235 lines
7.9 KiB
C
235 lines
7.9 KiB
C
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/*
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* Copyright 2017 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kvm_host.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_book3s_64.h>
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#include <asm/reg.h>
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#include <asm/ppc-opcode.h>
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static void emulate_tx_failure(struct kvm_vcpu *vcpu, u64 failure_cause)
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{
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u64 texasr, tfiar;
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u64 msr = vcpu->arch.shregs.msr;
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tfiar = vcpu->arch.regs.nip & ~0x3ull;
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texasr = (failure_cause << 56) | TEXASR_ABORT | TEXASR_FS | TEXASR_EXACT;
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if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
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texasr |= TEXASR_SUSP;
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if (msr & MSR_PR) {
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texasr |= TEXASR_PR;
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tfiar |= 1;
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}
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vcpu->arch.tfiar = tfiar;
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/* Preserve ROT and TL fields of existing TEXASR */
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vcpu->arch.texasr = (vcpu->arch.texasr & 0x3ffffff) | texasr;
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}
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/*
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* This gets called on a softpatch interrupt on POWER9 DD2.2 processors.
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* We expect to find a TM-related instruction to be emulated. The
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* instruction image is in vcpu->arch.emul_inst. If the guest was in
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* TM suspended or transactional state, the checkpointed state has been
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* reclaimed and is in the vcpu struct. The CPU is in virtual mode in
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* host context.
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*/
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int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
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{
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u32 instr = vcpu->arch.emul_inst;
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u64 msr = vcpu->arch.shregs.msr;
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u64 newmsr, bescr;
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int ra, rs;
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/*
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* rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit
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* in these instructions, so masking bit 31 out doesn't change these
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* instructions. For treclaim., tsr., and trechkpt. instructions if bit
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* 31 = 0 then they are per ISA invalid forms, however P9 UM, in section
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* 4.6.10 Book II Invalid Forms, informs specifically that ignoring bit
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* 31 is an acceptable way to handle these invalid forms that have
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* bit 31 = 0. Moreover, for emulation purposes both forms (w/ and wo/
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* bit 31 set) can generate a softpatch interrupt. Hence both forms
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* are handled below for these instructions so they behave the same way.
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*/
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switch (instr & PO_XOP_OPCODE_MASK) {
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case PPC_INST_RFID:
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/* XXX do we need to check for PR=0 here? */
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newmsr = vcpu->arch.shregs.srr1;
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/* should only get here for Sx -> T1 transition */
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WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
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MSR_TM_TRANSACTIONAL(newmsr) &&
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(newmsr & MSR_TM)));
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newmsr = sanitize_msr(newmsr);
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vcpu->arch.shregs.msr = newmsr;
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vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
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vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
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return RESUME_GUEST;
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case PPC_INST_RFEBB:
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if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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/* check EBB facility is available */
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if (!(vcpu->arch.hfscr & HFSCR_EBB)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
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/* generate a facility unavailable interrupt */
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vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
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((u64)FSCR_EBB_LG << 56);
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kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL);
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return RESUME_GUEST;
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}
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bescr = vcpu->arch.bescr;
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/* expect to see a S->T transition requested */
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WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
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((bescr >> 30) & 3) == 2));
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bescr &= ~BESCR_GE;
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if (instr & (1 << 11))
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bescr |= BESCR_GE;
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vcpu->arch.bescr = bescr;
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msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
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vcpu->arch.shregs.msr = msr;
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vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
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vcpu->arch.regs.nip = vcpu->arch.ebbrr;
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return RESUME_GUEST;
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case PPC_INST_MTMSRD:
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/* XXX do we need to check for PR=0 here? */
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rs = (instr >> 21) & 0x1f;
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newmsr = kvmppc_get_gpr(vcpu, rs);
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/* check this is a Sx -> T1 transition */
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WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
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MSR_TM_TRANSACTIONAL(newmsr) &&
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(newmsr & MSR_TM)));
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/* mtmsrd doesn't change LE */
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newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
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newmsr = sanitize_msr(newmsr);
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vcpu->arch.shregs.msr = newmsr;
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return RESUME_GUEST;
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/* ignore bit 31, see comment above */
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case (PPC_INST_TSR & PO_XOP_OPCODE_MASK):
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/* check for PR=1 and arch 2.06 bit set in PCR */
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if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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/* check for TM disabled in the HFSCR or MSR */
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if (!(vcpu->arch.hfscr & HFSCR_TM)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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if (!(msr & MSR_TM)) {
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/* generate a facility unavailable interrupt */
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vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
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((u64)FSCR_TM_LG << 56);
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kvmppc_book3s_queue_irqprio(vcpu,
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BOOK3S_INTERRUPT_FAC_UNAVAIL);
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return RESUME_GUEST;
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}
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/* Set CR0 to indicate previous transactional state */
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vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
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(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
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/* L=1 => tresume, L=0 => tsuspend */
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if (instr & (1 << 21)) {
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if (MSR_TM_SUSPENDED(msr))
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msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
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} else {
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if (MSR_TM_TRANSACTIONAL(msr))
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msr = (msr & ~MSR_TS_MASK) | MSR_TS_S;
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}
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vcpu->arch.shregs.msr = msr;
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return RESUME_GUEST;
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/* ignore bit 31, see comment above */
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case (PPC_INST_TRECLAIM & PO_XOP_OPCODE_MASK):
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/* check for TM disabled in the HFSCR or MSR */
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if (!(vcpu->arch.hfscr & HFSCR_TM)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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if (!(msr & MSR_TM)) {
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/* generate a facility unavailable interrupt */
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vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
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((u64)FSCR_TM_LG << 56);
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kvmppc_book3s_queue_irqprio(vcpu,
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BOOK3S_INTERRUPT_FAC_UNAVAIL);
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return RESUME_GUEST;
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}
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/* If no transaction active, generate TM bad thing */
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if (!MSR_TM_ACTIVE(msr)) {
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kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
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return RESUME_GUEST;
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}
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/* If failure was not previously recorded, recompute TEXASR */
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if (!(vcpu->arch.orig_texasr & TEXASR_FS)) {
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ra = (instr >> 16) & 0x1f;
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if (ra)
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ra = kvmppc_get_gpr(vcpu, ra) & 0xff;
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emulate_tx_failure(vcpu, ra);
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}
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copy_from_checkpoint(vcpu);
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/* Set CR0 to indicate previous transactional state */
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vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
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(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
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vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
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return RESUME_GUEST;
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/* ignore bit 31, see comment above */
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case (PPC_INST_TRECHKPT & PO_XOP_OPCODE_MASK):
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/* XXX do we need to check for PR=0 here? */
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/* check for TM disabled in the HFSCR or MSR */
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if (!(vcpu->arch.hfscr & HFSCR_TM)) {
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/* generate an illegal instruction interrupt */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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return RESUME_GUEST;
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}
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if (!(msr & MSR_TM)) {
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/* generate a facility unavailable interrupt */
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vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
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((u64)FSCR_TM_LG << 56);
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kvmppc_book3s_queue_irqprio(vcpu,
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BOOK3S_INTERRUPT_FAC_UNAVAIL);
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return RESUME_GUEST;
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}
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/* If transaction active or TEXASR[FS] = 0, bad thing */
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if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
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kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
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return RESUME_GUEST;
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}
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copy_to_checkpoint(vcpu);
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/* Set CR0 to indicate previous transactional state */
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vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
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(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
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vcpu->arch.shregs.msr = msr | MSR_TS_S;
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return RESUME_GUEST;
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}
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/* What should we do here? We didn't recognize the instruction */
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kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
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pr_warn_ratelimited("Unrecognized TM-related instruction %#x for emulation", instr);
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return RESUME_GUEST;
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}
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