73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
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#define __ASM_SH_CPU_SH4_DMA_SH7780_H
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#include <linux/sh_intc.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7730)
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#define DMTE0_IRQ evt2irq(0x800)
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#define DMTE4_IRQ evt2irq(0xb80)
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#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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#define DMTE0_IRQ evt2irq(0x800)
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#define DMTE4_IRQ evt2irq(0xb80)
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#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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#define DMTE0_IRQ evt2irq(0x640)
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#define DMTE4_IRQ evt2irq(0x780)
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#define DMAE0_IRQ evt2irq(0x6c0)
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#define SH_DMAC_BASE0 0xFF608020
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
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#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
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#define DMTE6_IRQ evt2irq(0x700)
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#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
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#define DMTE9_IRQ evt2irq(0x760)
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#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
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#define DMTE11_IRQ evt2irq(0xb20)
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#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
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#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMAC_BASE1 0xFDC08020
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
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#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
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#define DMTE6_IRQ evt2irq(0x700)
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#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
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#define DMTE9_IRQ evt2irq(0x760)
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#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
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#define DMTE11_IRQ evt2irq(0xb20)
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#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
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#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
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#define SH_DMAC_BASE0 0xFE008020
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#define SH_DMAC_BASE1 0xFDC08020
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define DMTE0_IRQ evt2irq(0x640)
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#define DMTE4_IRQ evt2irq(0x780)
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#define DMTE6_IRQ evt2irq(0x7c0)
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#define DMTE8_IRQ evt2irq(0xd80)
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#define DMTE9_IRQ evt2irq(0xda0)
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#define DMTE10_IRQ evt2irq(0xdc0)
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#define DMTE11_IRQ evt2irq(0xde0)
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#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
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#define SH_DMAC_BASE0 0xFC808020
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#define SH_DMAC_BASE1 0xFC818020
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#else /* SH7785 */
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#define DMTE0_IRQ evt2irq(0x620)
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#define DMTE4_IRQ evt2irq(0x6a0)
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#define DMTE6_IRQ evt2irq(0x880)
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#define DMTE8_IRQ evt2irq(0x8c0)
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#define DMTE9_IRQ evt2irq(0x8e0)
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#define DMTE10_IRQ evt2irq(0x900)
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#define DMTE11_IRQ evt2irq(0x920)
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#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
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#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
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#define SH_DMAC_BASE0 0xFC808020
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#define SH_DMAC_BASE1 0xFCC08020
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#endif
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#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
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