385 lines
8.6 KiB
C
385 lines
8.6 KiB
C
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/*
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* Performance event support framework for SuperH hardware counters.
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*
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* Copyright (C) 2009 Paul Mundt
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*
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* Heavily based on the x86 and PowerPC implementations.
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*
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* x86:
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* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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*
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* ppc:
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/perf_event.h>
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#include <linux/export.h>
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#include <asm/processor.h>
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struct cpu_hw_events {
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struct perf_event *events[MAX_HWEVENTS];
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unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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};
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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static struct sh_pmu *sh_pmu __read_mostly;
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/* Number of perf_events counting hardware events */
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static atomic_t num_events;
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/* Used to avoid races in calling reserve/release_pmc_hardware */
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static DEFINE_MUTEX(pmc_reserve_mutex);
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/*
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* Stub these out for now, do something more profound later.
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*/
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int reserve_pmc_hardware(void)
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{
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return 0;
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}
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void release_pmc_hardware(void)
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{
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}
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static inline int sh_pmu_initialized(void)
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{
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return !!sh_pmu;
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}
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const char *perf_pmu_name(void)
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{
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if (!sh_pmu)
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return NULL;
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return sh_pmu->name;
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}
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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int perf_num_counters(void)
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{
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if (!sh_pmu)
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return 0;
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return sh_pmu->num_events;
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}
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EXPORT_SYMBOL_GPL(perf_num_counters);
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/*
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* Release the PMU if this is the last perf_event.
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*/
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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if (!atomic_add_unless(&num_events, -1, 1)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_dec_return(&num_events) == 0)
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release_pmc_hardware();
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mutex_unlock(&pmc_reserve_mutex);
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}
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}
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static int hw_perf_cache_event(int config, int *evp)
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{
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unsigned long type, op, result;
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int ev;
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if (!sh_pmu->cache_events)
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return -EINVAL;
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/* unpack config */
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type = config & 0xff;
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op = (config >> 8) & 0xff;
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result = (config >> 16) & 0xff;
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if (type >= PERF_COUNT_HW_CACHE_MAX ||
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op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ev = (*sh_pmu->cache_events)[type][op][result];
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if (ev == 0)
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return -EOPNOTSUPP;
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if (ev == -1)
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return -EINVAL;
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*evp = ev;
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return 0;
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}
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static int __hw_perf_event_init(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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struct hw_perf_event *hwc = &event->hw;
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int config = -1;
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int err;
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if (!sh_pmu_initialized())
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return -ENODEV;
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/*
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* See if we need to reserve the counter.
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*
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* If no events are currently in use, then we have to take a
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* mutex to ensure that we don't race with another task doing
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* reserve_pmc_hardware or release_pmc_hardware.
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*/
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err = 0;
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if (!atomic_inc_not_zero(&num_events)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_read(&num_events) == 0 &&
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reserve_pmc_hardware())
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err = -EBUSY;
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else
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atomic_inc(&num_events);
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mutex_unlock(&pmc_reserve_mutex);
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}
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if (err)
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return err;
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event->destroy = hw_perf_event_destroy;
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switch (attr->type) {
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case PERF_TYPE_RAW:
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config = attr->config & sh_pmu->raw_event_mask;
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break;
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case PERF_TYPE_HW_CACHE:
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err = hw_perf_cache_event(attr->config, &config);
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if (err)
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return err;
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break;
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case PERF_TYPE_HARDWARE:
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if (attr->config >= sh_pmu->max_events)
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return -EINVAL;
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config = sh_pmu->event_map(attr->config);
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break;
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}
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if (config == -1)
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return -EINVAL;
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hwc->config |= config;
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return 0;
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}
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static void sh_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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int shift = 0;
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/*
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* Depending on the counter configuration, they may or may not
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* be chained, in which case the previous counter value can be
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* updated underneath us if the lower-half overflows.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic counter atomically.
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*
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* As there is no interrupt associated with the overflow events,
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* this is the simplest approach for maintaining consistency.
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*/
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = sh_pmu->read(idx);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (counter-)time and add that to the generic counter.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count.
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*/
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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}
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static void sh_pmu_stop(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (!(event->hw.state & PERF_HES_STOPPED)) {
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sh_pmu->disable(hwc, idx);
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cpuc->events[idx] = NULL;
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event->hw.state |= PERF_HES_STOPPED;
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}
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if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
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sh_perf_event_update(event, &event->hw, idx);
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event->hw.state |= PERF_HES_UPTODATE;
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}
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}
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static void sh_pmu_start(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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cpuc->events[idx] = event;
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event->hw.state = 0;
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sh_pmu->enable(hwc, idx);
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}
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static void sh_pmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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sh_pmu_stop(event, PERF_EF_UPDATE);
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__clear_bit(event->hw.idx, cpuc->used_mask);
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perf_event_update_userpage(event);
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}
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static int sh_pmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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int ret = -EAGAIN;
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perf_pmu_disable(event->pmu);
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if (__test_and_set_bit(idx, cpuc->used_mask)) {
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idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
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if (idx == sh_pmu->num_events)
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goto out;
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__set_bit(idx, cpuc->used_mask);
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hwc->idx = idx;
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}
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sh_pmu->disable(hwc, idx);
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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sh_pmu_start(event, PERF_EF_RELOAD);
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perf_event_update_userpage(event);
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ret = 0;
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out:
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perf_pmu_enable(event->pmu);
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return ret;
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}
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static void sh_pmu_read(struct perf_event *event)
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{
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sh_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int sh_pmu_event_init(struct perf_event *event)
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{
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int err;
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/* does not support taken branch sampling */
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if (has_branch_stack(event))
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return -EOPNOTSUPP;
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switch (event->attr.type) {
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case PERF_TYPE_RAW:
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case PERF_TYPE_HW_CACHE:
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case PERF_TYPE_HARDWARE:
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err = __hw_perf_event_init(event);
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break;
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default:
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return -ENOENT;
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}
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if (unlikely(err)) {
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if (event->destroy)
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event->destroy(event);
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}
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return err;
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}
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static void sh_pmu_enable(struct pmu *pmu)
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{
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if (!sh_pmu_initialized())
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return;
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sh_pmu->enable_all();
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}
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static void sh_pmu_disable(struct pmu *pmu)
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{
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if (!sh_pmu_initialized())
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return;
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sh_pmu->disable_all();
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}
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static struct pmu pmu = {
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.pmu_enable = sh_pmu_enable,
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.pmu_disable = sh_pmu_disable,
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.event_init = sh_pmu_event_init,
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.add = sh_pmu_add,
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.del = sh_pmu_del,
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.start = sh_pmu_start,
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.stop = sh_pmu_stop,
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.read = sh_pmu_read,
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};
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static int sh_pmu_prepare_cpu(unsigned int cpu)
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{
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struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
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memset(cpuhw, 0, sizeof(struct cpu_hw_events));
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return 0;
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}
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int register_sh_pmu(struct sh_pmu *_pmu)
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{
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if (sh_pmu)
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return -EBUSY;
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sh_pmu = _pmu;
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pr_info("Performance Events: %s support registered\n", _pmu->name);
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/*
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* All of the on-chip counters are "limited", in that they have
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* no interrupts, and are therefore unable to do sampling without
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* further work and timer assistance.
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*/
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pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
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WARN_ON(_pmu->num_events > MAX_HWEVENTS);
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perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
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cpuhp_setup_state(CPUHP_PERF_SUPERH, "PERF_SUPERH", sh_pmu_prepare_cpu,
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NULL);
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return 0;
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}
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