62 lines
2 KiB
C
62 lines
2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SPARC64_BARRIER_H
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#define __SPARC64_BARRIER_H
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/* These are here in an effort to more fully work around Spitfire Errata
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* branch, the chip can stop executing instructions until a trap occurs.
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* Therefore, if interrupts are disabled, the chip can hang forever.
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*
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* It used to be believed that the memory barrier had to be right in the
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* delay slot, but a case has been traced recently wherein the memory barrier
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* was one instruction after the branch delay slot and the chip still hung.
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* The offending sequence was the following in sym_wakeup_done() of the
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* sym53c8xx_2 driver:
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*
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* call sym_ccb_from_dsa, 0
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* movge %icc, 0, %l0
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* brz,pn %o0, .LL1303
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* mov %o0, %l2
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* membar #LoadLoad
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*
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* The branch has to be mispredicted for the bug to occur. Therefore, we put
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* the memory barrier explicitly into a "branch always, predicted taken"
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* delay slot to avoid the problem case.
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*/
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#define membar_safe(type) \
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do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
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" membar " type "\n" \
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"1:\n" \
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: : : "memory"); \
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} while (0)
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/* The kernel always executes in TSO memory model these days,
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* and furthermore most sparc64 chips implement more stringent
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* memory ordering than required by the specifications.
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*/
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#define mb() membar_safe("#StoreLoad")
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#define rmb() __asm__ __volatile__("":::"memory")
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#define wmb() __asm__ __volatile__("":::"memory")
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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#include <asm-generic/barrier.h>
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#endif /* !(__SPARC64_BARRIER_H) */
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