60 lines
2 KiB
C
60 lines
2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _SPARC_CACHEFLUSH_H
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#define _SPARC_CACHEFLUSH_H
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#include <asm/cachetlb_32.h>
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#define flush_cache_all() \
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sparc32_cachetlb_ops->cache_all()
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#define flush_cache_mm(mm) \
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sparc32_cachetlb_ops->cache_mm(mm)
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#define flush_cache_dup_mm(mm) \
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sparc32_cachetlb_ops->cache_mm(mm)
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#define flush_cache_range(vma,start,end) \
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sparc32_cachetlb_ops->cache_range(vma, start, end)
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#define flush_cache_page(vma,addr,pfn) \
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sparc32_cachetlb_ops->cache_page(vma, addr)
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#define flush_icache_range(start, end) do { } while (0)
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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#define __flush_page_to_ram(addr) \
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sparc32_cachetlb_ops->page_to_ram(addr)
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#define flush_sig_insns(mm,insn_addr) \
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sparc32_cachetlb_ops->sig_insns(mm, insn_addr)
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#define flush_page_for_dma(addr) \
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sparc32_cachetlb_ops->page_for_dma(addr)
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void sparc_flush_page_to_ram(struct page *page);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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/* When a context switch happens we must flush all user windows so that
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* the windows of the current process are flushed onto its stack. This
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* way the windows are all clean for the next process and the stack
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* frames are up to date.
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*/
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void flush_user_windows(void);
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void kill_user_windows(void);
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void flushw_all(void);
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#endif /* _SPARC_CACHEFLUSH_H */
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