92 lines
2 KiB
C
92 lines
2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6877-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status mfgcfg_pwr_stat = GATE_PWR_STAT(0xEF8,
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0xEFC, INV_OFS, 0x3f, 0x3f);
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static const struct mtk_gate_regs mfgcfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFGCFG(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mfgcfg_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mfgcfg_pwr_stat, \
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}
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static const struct mtk_gate mfgcfg_clks[] = {
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GATE_MFGCFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
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"mfg_internal2_ck"/* parent */, 0),
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};
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static int clk_mt6877_mfgcfg_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
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mtk_clk_register_gates(node, mfgcfg_clks, ARRAY_SIZE(mfgcfg_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6877_mfgcfg[] = {
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{ .compatible = "mediatek,mt6877-mfgcfg", },
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{}
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};
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static struct platform_driver clk_mt6877_mfgcfg_drv = {
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.probe = clk_mt6877_mfgcfg_probe,
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.driver = {
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.name = "clk-mt6877-mfgcfg",
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.of_match_table = of_match_clk_mt6877_mfgcfg,
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},
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};
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static int __init clk_mt6877_mfgcfg_init(void)
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{
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return platform_driver_register(&clk_mt6877_mfgcfg_drv);
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}
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arch_initcall(clk_mt6877_mfgcfg_init);
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