538 lines
8.4 KiB
C
538 lines
8.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/syscore_ops.h>
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#include <linux/version.h>
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#include "clkchk-mt6768.h"
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#define WARN_ON_CHECK_FAIL 0
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#define CLKDBG_CCF_API_4_4 1
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#define TAG "[clkchk] "
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#define clk_warn(fmt, args...) pr_notice(TAG fmt, ##args)
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#if !CLKDBG_CCF_API_4_4
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/* backward compatible */
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static const char *clk_hw_get_name(const struct clk_hw *hw)
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{
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return __clk_get_name(hw->clk);
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}
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static bool clk_hw_is_prepared(const struct clk_hw *hw)
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{
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return __clk_is_prepared(hw->clk);
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}
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static bool clk_hw_is_enabled(const struct clk_hw *hw)
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{
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return __clk_is_enabled(hw->clk);
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}
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#endif /* !CLKDBG_CCF_API_4_4 */
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static const char * const *get_all_clk_names(void)
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{
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static const char * const clks[] = {
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/* PLLs */
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"armpll",
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"armpll_l",
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"ccipll",
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"mainpll",
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"univ2pll",
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"msdcpll",
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"mfgpll",
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"mmpll",
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"mpll",
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"apll1",
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/* TOP */
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"syspll_ck",
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"syspll_d2",
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"syspll1_d2",
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"syspll1_d4",
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"syspll1_d8",
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"syspll1_d16",
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"syspll_d3",
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"syspll2_d2",
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"syspll2_d4",
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"syspll2_d8",
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"syspll_d5",
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"syspll3_d2",
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"syspll3_d4",
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"syspll_d7",
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"syspll4_d2",
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"syspll4_d4",
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"usb20_192m_ck",
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"usb20_192m_d4",
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"usb20_192m_d8",
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"usb20_192m_d16",
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"usb20_192m_d32",
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"univpll",
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"univpll_d2",
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"univpll1_d2",
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"univpll1_d4",
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"univpll_d3",
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"univpll2_d2",
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"univpll2_d4",
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"univpll2_d8",
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"univpll2_d32",
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"univpll_d5",
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"univpll3_d2",
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"univpll3_d4",
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"mmpll_ck",
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"mmpll_d2",
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"mpll_ck",
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"mpll_104m_div",
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"mpll_52m_div",
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"mfgpll_ck",
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"msdcpll_ck",
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"msdcpll_d2",
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"apll1_ck",
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"apll1_d2",
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"apll1_d4",
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"apll1_d8",
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"ulposc1_ck",
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"ulposc1_d2",
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"ulposc1_d4",
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"ulposc1_d8",
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"ulposc1_d16",
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"ulposc1_d32",
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"f_frtc_ck",
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"clk_26m_ck",
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"dmpll_ck",
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"axi_sel",
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"mem_sel",
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"mm_sel",
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"scp_sel",
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"mfg_sel",
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"atb_sel",
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"camtg_sel",
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"camtg1_sel",
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"camtg2_sel",
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"camtg3_sel",
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"uart_sel",
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"spi_sel",
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"msdc5hclk",
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"msdc50_0_sel",
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"msdc30_1_sel",
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"audio_sel",
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"aud_intbus_sel",
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"aud_1_sel",
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"aud_engen1_sel",
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"disp_pwm_sel",
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"sspm_sel",
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"dxcc_sel",
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"usb_top_sel",
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"spm_sel",
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"i2c_sel",
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"pwm_sel",
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"seninf_sel",
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"aes_fde_sel",
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"ulposc_sel",
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"camtm_sel",
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"venc_sel",
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"cam_sel",
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/* INFRACFG */
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"ifr_axi_dis",
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"ifr_pmic_tmr",
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"ifr_pmic_ap",
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"ifr_pmic_md",
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"ifr_pmic_conn",
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"ifr_scp_core",
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"ifr_sej",
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"ifr_apxgpt",
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"ifr_icusb",
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"ifr_gce",
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"ifr_therm",
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"ifr_i2c_ap",
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"ifr_i2c_ccu",
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"ifr_i2c_sspm",
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"ifr_i2c_rsv",
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"ifr_pwm_hclk",
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"ifr_pwm1",
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"ifr_pwm2",
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"ifr_pwm3",
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"ifr_pwm4",
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"ifr_pwm5",
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"ifr_pwm",
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"ifr_uart0",
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"ifr_uart1",
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"ifr_gce_26m",
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"ifr_dma",
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"ifr_btif",
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"ifr_spi0",
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"ifr_msdc0",
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"ifr_msdc1",
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"ifr_dvfsrc",
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"ifr_gcpu",
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"ifr_trng",
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"ifr_auxadc",
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"ifr_cpum",
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"ifr_ccif1_ap",
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"ifr_ccif1_md",
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"ifr_auxadc_md",
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"ifr_ap_dma",
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"ifr_xiu",
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"ifr_dapc",
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"ifr_ccif_ap",
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"ifr_debugtop",
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"ifr_audio",
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"ifr_ccif_md",
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"ifr_secore",
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"ifr_dxcc_ao",
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"ifr_dramc26",
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"ifr_pwmfb",
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"ifr_disp_pwm",
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"ifr_cldmabclk",
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"ifr_audio26m",
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"ifr_spi1",
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"ifr_i2c4",
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"ifr_mdtemp",
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"ifr_spi2",
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"ifr_spi3",
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"ifr_hf_fsspm",
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"ifr_i2c5",
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"ifr_i2c5a",
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"ifr_i2c5_imm",
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"ifr_i2c1a",
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"ifr_i2c1_imm",
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"ifr_i2c2a",
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"ifr_i2c2_imm",
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"ifr_spi4",
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"ifr_spi5",
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"ifr_cq_dma",
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"ifr_faes_fde_ck",
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"ifr_msdc0f",
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"ifr_msdc1sf",
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"ifr_sspm_26m",
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"ifr_sspm_32k",
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"ifr_i2c6",
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"ifr_ap_msdc0",
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"ifr_md_msdc0",
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"ifr_msdc0_clk",
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"ifr_msdc1_clk",
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"ifr_sej_f13m",
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"ifr_aes",
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"ifr_mcu_pm_bclk",
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"ifr_ccif2_ap",
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"ifr_ccif2_md",
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"ifr_ccif3_ap",
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"ifr_ccif3_md",
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/* PERICFG */
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"periaxi_disable",
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/* AUDIO */
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"aud_afe",
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"aud_22m",
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"aud_24m",
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"aud_apll_tuner",
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"aud_adc",
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"aud_dac",
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"aud_dac_predis",
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"aud_tml",
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"aud_i2s1_bclk",
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"aud_i2s2_bclk",
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"aud_i2s3_bclk",
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"aud_i2s4_bclk",
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/* CAM */
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"cam_larb3",
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"cam_dfp_vad",
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"cam",
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"camtg",
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"cam_seninf",
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"camsv0",
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"camsv1",
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"camsv2",
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"cam_ccu",
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/* IMG */
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"img_larb2",
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"img_dip",
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"img_fdvt",
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"img_dpe",
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"img_rsc",
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/* MFG */
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"mfgcfg_bg3d",
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/* MM */
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"mm_mdp_rdma0",
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"mm_mdp_ccorr0",
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"mm_mdp_rsz0",
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"mm_mdp_rsz1",
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"mm_mdp_tdshp0",
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"mm_mdp_wrot0",
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"mm_mdp_wdma0",
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"mm_disp_ovl0",
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"mm_disp_ovl0_2l",
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"mm_disp_rsz0",
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"mm_disp_rdma0",
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"mm_disp_wdma0",
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"mm_disp_color0",
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"mm_disp_ccorr0",
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"mm_disp_aal0",
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"mm_disp_gamma0",
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"mm_disp_dither0",
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"mm_dsi0",
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"mm_fake_eng",
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"mm_smi_common",
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"mm_smi_larb0",
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"mm_smi_comm0",
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"mm_smi_comm1",
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"mm_cam_mdp_ck",
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"mm_smi_img_ck",
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"mm_smi_cam_ck",
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"mm_smi_venc_ck",
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"mm_smi_vdec_ck",
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"mm_img_dl_relay",
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"mm_imgdl_async",
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"mm_dig_dsi_ck",
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"mm_hrtwt",
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/* VENC */
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"venc_set0_larb",
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"venc_set1_venc",
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"jpgenc",
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/* VDEC */
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"vdec_cken",
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"vdec_active",
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"vdec_cken_eng",
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"vdec_larb1_cken",
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/* MIPI */
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"mipi0a_csr_0a",
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"mipi0b_csr_0b",
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"mipi1a_csr_1a",
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"mipi1b_csr_1b",
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"mipi2a_csr_2a",
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"mipi2b_csr_2b",
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/* GCE */
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"gce",
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/* APMIXED 26MCK */
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"apmixed_ssusb26m",
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"apmixed_appll26m",
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"apmixed_mipic026m",
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"apmixed_mdpll26m",
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"apmixed_mmsys26m",
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"apmixed_ufs26m",
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"apmixed_mipic126m",
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"apmixed_mempll26m",
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"apmixed_lvpll26m",
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"apmixed_mipid026m",
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/* end */
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NULL
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};
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return clks;
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}
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static const char *ccf_state(struct clk_hw *hw)
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{
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if (__clk_get_enable_count(hw->clk))
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return "enabled";
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if (clk_hw_is_prepared(hw))
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return "prepared";
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return "disabled";
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}
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void print_enabled_clks(void)
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{
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const char * const *cn = get_all_clk_names();
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clk_warn("enabled clks:\n");
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for (; *cn; cn++) {
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struct clk *c = __clk_lookup(*cn);
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struct clk_hw *c_hw = __clk_get_hw(c);
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struct clk_hw *p_hw;
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if (IS_ERR_OR_NULL(c) || !c_hw)
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continue;
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p_hw = clk_hw_get_parent(c_hw);
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if (!p_hw)
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continue;
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if (!clk_hw_is_prepared(c_hw) && !__clk_get_enable_count(c))
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continue;
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clk_warn("[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
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clk_hw_get_name(c_hw),
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ccf_state(c_hw),
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clk_hw_is_prepared(c_hw),
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__clk_get_enable_count(c),
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clk_hw_get_rate(c_hw),
|
||
|
|
p_hw ? clk_hw_get_name(p_hw) : "- ");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void check_pll_off(void)
|
||
|
|
{
|
||
|
|
static const char * const off_pll_names[] = {
|
||
|
|
"univ2pll",
|
||
|
|
"mfgpll",
|
||
|
|
"apll1",
|
||
|
|
"mmpll",
|
||
|
|
"msdcpll",
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk *off_plls[ARRAY_SIZE(off_pll_names)];
|
||
|
|
|
||
|
|
struct clk **c;
|
||
|
|
int invalid = 0;
|
||
|
|
char buf[128] = {0};
|
||
|
|
int n = 0;
|
||
|
|
|
||
|
|
if (!off_plls[0]) {
|
||
|
|
const char * const *pn;
|
||
|
|
|
||
|
|
for (pn = off_pll_names, c = off_plls; *pn; pn++, c++)
|
||
|
|
*c = __clk_lookup(*pn);
|
||
|
|
}
|
||
|
|
|
||
|
|
for (c = off_plls; *c; c++) {
|
||
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
||
|
|
|
||
|
|
if (!c_hw)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (!clk_hw_is_enabled(c_hw))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
n += snprintf(buf + n, sizeof(buf) - n, "%s ",
|
||
|
|
clk_hw_get_name(c_hw));
|
||
|
|
|
||
|
|
invalid++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (invalid) {
|
||
|
|
clk_warn("suspend warning: unexpected unclosed PLL: %s\n", buf);
|
||
|
|
print_enabled_clks();
|
||
|
|
|
||
|
|
#if WARN_ON_CHECK_FAIL
|
||
|
|
WARN_ON(1);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void check_mtcmos_off(void)
|
||
|
|
{
|
||
|
|
static const char * const off_mtcmos_names[] = {
|
||
|
|
/* "pg_md1", */
|
||
|
|
"pg_conn",
|
||
|
|
/* "pg_dpy", */
|
||
|
|
"pg_dis",
|
||
|
|
"pg_mfg",
|
||
|
|
"pg_isp",
|
||
|
|
/* "pg_ifr", */
|
||
|
|
"pg_mfg_core0",
|
||
|
|
"pg_mfg_core1",
|
||
|
|
"pg_mfg_async",
|
||
|
|
"pg_cam",
|
||
|
|
"pg_venc",
|
||
|
|
"pg_vdec",
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk *off_mtcmos[ARRAY_SIZE(off_mtcmos_names)];
|
||
|
|
|
||
|
|
struct clk **c;
|
||
|
|
int invalid = 0;
|
||
|
|
char buf[128] = {0};
|
||
|
|
int n = 0;
|
||
|
|
|
||
|
|
if (!off_mtcmos[0]) {
|
||
|
|
const char * const *pn;
|
||
|
|
|
||
|
|
for (pn = off_mtcmos_names, c = off_mtcmos; *pn; pn++, c++)
|
||
|
|
*c = __clk_lookup(*pn);
|
||
|
|
}
|
||
|
|
|
||
|
|
for (c = off_mtcmos; *c; c++) {
|
||
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
||
|
|
|
||
|
|
if (!c_hw)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (!clk_hw_is_prepared(c_hw) && !clk_hw_is_enabled(c_hw))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
n += snprintf(buf + n, sizeof(buf) - n, "%s ",
|
||
|
|
clk_hw_get_name(c_hw));
|
||
|
|
|
||
|
|
invalid++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (invalid) {
|
||
|
|
clk_warn("suspend warning: unclosed MTCMOS: %s\n", buf);
|
||
|
|
|
||
|
|
#if WARN_ON_CHECK_FAIL
|
||
|
|
WARN_ON(1);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void print_enabled_clks_once(void)
|
||
|
|
{
|
||
|
|
static bool first_flag = true;
|
||
|
|
|
||
|
|
if (first_flag) {
|
||
|
|
first_flag = false;
|
||
|
|
print_enabled_clks();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int clkchk_syscore_suspend(void)
|
||
|
|
{
|
||
|
|
check_pll_off();
|
||
|
|
check_mtcmos_off();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void clkchk_syscore_resume(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct syscore_ops clkchk_syscore_ops = {
|
||
|
|
.suspend = clkchk_syscore_suspend,
|
||
|
|
.resume = clkchk_syscore_resume,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init clkchk_init(void)
|
||
|
|
{
|
||
|
|
if (!of_machine_is_compatible("mediatek,MT6768"))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
register_syscore_ops(&clkchk_syscore_ops);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
subsys_initcall(clkchk_init);
|