410 lines
10 KiB
C
410 lines
10 KiB
C
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/*
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* Copyright (C) STMicroelectronics SA 2017
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* Author: Fabien Dessenne <fabien.dessenne@st.com>
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/bitrev.h>
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#include <linux/clk.h>
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#include <linux/crc32poly.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <crypto/internal/hash.h>
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#include <asm/unaligned.h>
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#define DRIVER_NAME "stm32-crc32"
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#define CHKSUM_DIGEST_SIZE 4
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#define CHKSUM_BLOCK_SIZE 1
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/* Registers */
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#define CRC_DR 0x00000000
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#define CRC_CR 0x00000008
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#define CRC_INIT 0x00000010
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#define CRC_POL 0x00000014
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/* Registers values */
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#define CRC_CR_RESET BIT(0)
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#define CRC_CR_REV_IN_WORD (BIT(6) | BIT(5))
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#define CRC_CR_REV_IN_BYTE BIT(5)
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#define CRC_CR_REV_OUT BIT(7)
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#define CRC32C_INIT_DEFAULT 0xFFFFFFFF
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#define CRC_AUTOSUSPEND_DELAY 50
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struct stm32_crc {
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struct list_head list;
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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};
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struct stm32_crc_list {
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struct list_head dev_list;
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spinlock_t lock; /* protect dev_list */
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};
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static struct stm32_crc_list crc_list = {
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.dev_list = LIST_HEAD_INIT(crc_list.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
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};
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struct stm32_crc_ctx {
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u32 key;
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u32 poly;
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};
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struct stm32_crc_desc_ctx {
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u32 partial; /* crc32c: partial in first 4 bytes of that struct */
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};
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static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
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{
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struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
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mctx->key = 0;
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mctx->poly = CRC32_POLY_LE;
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return 0;
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}
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static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
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{
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struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
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mctx->key = CRC32C_INIT_DEFAULT;
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mctx->poly = CRC32C_POLY_LE;
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return 0;
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}
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static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
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unsigned int keylen)
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{
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struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
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if (keylen != sizeof(u32)) {
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crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
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return -EINVAL;
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}
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mctx->key = get_unaligned_le32(key);
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return 0;
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}
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static struct stm32_crc *stm32_crc_get_next_crc(void)
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{
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struct stm32_crc *crc;
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spin_lock_bh(&crc_list.lock);
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crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
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if (crc)
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list_move_tail(&crc->list, &crc_list.dev_list);
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spin_unlock_bh(&crc_list.lock);
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return crc;
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}
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static int stm32_crc_init(struct shash_desc *desc)
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{
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struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
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struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
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struct stm32_crc *crc;
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crc = stm32_crc_get_next_crc();
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if (!crc)
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return -ENODEV;
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pm_runtime_get_sync(crc->dev);
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/* Reset, set key, poly and configure in bit reverse mode */
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writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
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writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
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writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
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crc->regs + CRC_CR);
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/* Store partial result */
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ctx->partial = readl_relaxed(crc->regs + CRC_DR);
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pm_runtime_mark_last_busy(crc->dev);
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pm_runtime_put_autosuspend(crc->dev);
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return 0;
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}
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static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
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unsigned int length)
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{
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struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
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struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
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struct stm32_crc *crc;
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crc = stm32_crc_get_next_crc();
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if (!crc)
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return -ENODEV;
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pm_runtime_get_sync(crc->dev);
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/*
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* Restore previously calculated CRC for this context as init value
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* Restore polynomial configuration
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* Configure in register for word input data,
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* Configure out register in reversed bit mode data.
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*/
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writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
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writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
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writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
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crc->regs + CRC_CR);
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if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
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/* Configure for byte data */
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writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
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crc->regs + CRC_CR);
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while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
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writeb_relaxed(*d8++, crc->regs + CRC_DR);
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length--;
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}
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/* Configure for word data */
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writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
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crc->regs + CRC_CR);
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}
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for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
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writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
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if (length) {
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/* Configure for byte data */
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writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
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crc->regs + CRC_CR);
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while (length--)
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writeb_relaxed(*d8++, crc->regs + CRC_DR);
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}
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/* Store partial result */
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ctx->partial = readl_relaxed(crc->regs + CRC_DR);
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pm_runtime_mark_last_busy(crc->dev);
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pm_runtime_put_autosuspend(crc->dev);
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return 0;
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}
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static int stm32_crc_final(struct shash_desc *desc, u8 *out)
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{
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struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
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struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
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/* Send computed CRC */
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put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
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~ctx->partial : ctx->partial, out);
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return 0;
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}
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static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
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unsigned int length, u8 *out)
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{
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return stm32_crc_update(desc, data, length) ?:
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stm32_crc_final(desc, out);
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}
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static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
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unsigned int length, u8 *out)
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{
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return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
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}
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static unsigned int refcnt;
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static DEFINE_MUTEX(refcnt_lock);
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static struct shash_alg algs[] = {
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/* CRC-32 */
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{
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.setkey = stm32_crc_setkey,
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.init = stm32_crc_init,
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.update = stm32_crc_update,
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.final = stm32_crc_final,
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.finup = stm32_crc_finup,
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.digest = stm32_crc_digest,
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.descsize = sizeof(struct stm32_crc_desc_ctx),
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.digestsize = CHKSUM_DIGEST_SIZE,
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.base = {
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.cra_name = "crc32",
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.cra_driver_name = DRIVER_NAME,
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.cra_priority = 200,
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.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
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.cra_blocksize = CHKSUM_BLOCK_SIZE,
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.cra_alignmask = 3,
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.cra_ctxsize = sizeof(struct stm32_crc_ctx),
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.cra_module = THIS_MODULE,
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.cra_init = stm32_crc32_cra_init,
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}
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},
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/* CRC-32Castagnoli */
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{
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.setkey = stm32_crc_setkey,
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.init = stm32_crc_init,
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.update = stm32_crc_update,
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.final = stm32_crc_final,
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.finup = stm32_crc_finup,
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.digest = stm32_crc_digest,
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.descsize = sizeof(struct stm32_crc_desc_ctx),
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.digestsize = CHKSUM_DIGEST_SIZE,
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.base = {
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.cra_name = "crc32c",
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.cra_driver_name = DRIVER_NAME,
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.cra_priority = 200,
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.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
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.cra_blocksize = CHKSUM_BLOCK_SIZE,
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.cra_alignmask = 3,
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.cra_ctxsize = sizeof(struct stm32_crc_ctx),
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.cra_module = THIS_MODULE,
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.cra_init = stm32_crc32c_cra_init,
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}
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}
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};
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static int stm32_crc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct stm32_crc *crc;
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struct resource *res;
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int ret;
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crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
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if (!crc)
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return -ENOMEM;
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crc->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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crc->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(crc->regs)) {
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dev_err(dev, "Cannot map CRC IO\n");
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return PTR_ERR(crc->regs);
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}
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crc->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(crc->clk)) {
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dev_err(dev, "Could not get clock\n");
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return PTR_ERR(crc->clk);
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}
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ret = clk_prepare_enable(crc->clk);
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if (ret) {
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dev_err(crc->dev, "Failed to enable clock\n");
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return ret;
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}
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pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_get_noresume(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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platform_set_drvdata(pdev, crc);
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spin_lock(&crc_list.lock);
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list_add(&crc->list, &crc_list.dev_list);
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spin_unlock(&crc_list.lock);
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mutex_lock(&refcnt_lock);
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if (!refcnt) {
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ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
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if (ret) {
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mutex_unlock(&refcnt_lock);
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dev_err(dev, "Failed to register\n");
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clk_disable_unprepare(crc->clk);
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return ret;
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}
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}
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refcnt++;
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mutex_unlock(&refcnt_lock);
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dev_info(dev, "Initialized\n");
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pm_runtime_put_sync(dev);
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return 0;
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}
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static int stm32_crc_remove(struct platform_device *pdev)
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{
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struct stm32_crc *crc = platform_get_drvdata(pdev);
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int ret = pm_runtime_get_sync(crc->dev);
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if (ret < 0)
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return ret;
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spin_lock(&crc_list.lock);
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list_del(&crc->list);
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spin_unlock(&crc_list.lock);
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mutex_lock(&refcnt_lock);
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if (!--refcnt)
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crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
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mutex_unlock(&refcnt_lock);
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pm_runtime_disable(crc->dev);
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pm_runtime_put_noidle(crc->dev);
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clk_disable_unprepare(crc->clk);
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return 0;
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}
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#ifdef CONFIG_PM
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static int stm32_crc_runtime_suspend(struct device *dev)
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{
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struct stm32_crc *crc = dev_get_drvdata(dev);
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clk_disable_unprepare(crc->clk);
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return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int stm32_crc_runtime_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct stm32_crc *crc = dev_get_drvdata(dev);
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(crc->clk);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(crc->dev, "Failed to prepare_enable clock\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops stm32_crc_pm_ops = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||
|
|
pm_runtime_force_resume)
|
||
|
|
SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
|
||
|
|
stm32_crc_runtime_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id stm32_dt_ids[] = {
|
||
|
|
{ .compatible = "st,stm32f7-crc", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, stm32_dt_ids);
|
||
|
|
|
||
|
|
static struct platform_driver stm32_crc_driver = {
|
||
|
|
.probe = stm32_crc_probe,
|
||
|
|
.remove = stm32_crc_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = DRIVER_NAME,
|
||
|
|
.pm = &stm32_crc_pm_ops,
|
||
|
|
.of_match_table = stm32_dt_ids,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(stm32_crc_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
|
||
|
|
MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
|
||
|
|
MODULE_LICENSE("GPL");
|