431 lines
10 KiB
C
431 lines
10 KiB
C
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/*
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* Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung EXYNOS5 SoC series G-Scaler driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 2 of the License,
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* or (at your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "gsc-core.h"
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void gsc_hw_set_sw_reset(struct gsc_dev *dev)
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{
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writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET);
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}
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int gsc_wait_reset(struct gsc_dev *dev)
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{
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unsigned long end = jiffies + msecs_to_jiffies(50);
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u32 cfg;
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while (time_before(jiffies, end)) {
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cfg = readl(dev->regs + GSC_SW_RESET);
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if (!cfg)
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return 0;
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usleep_range(10, 20);
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}
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return -EBUSY;
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}
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void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask)
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{
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u32 cfg;
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cfg = readl(dev->regs + GSC_IRQ);
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if (mask)
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cfg |= GSC_IRQ_FRMDONE_MASK;
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else
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cfg &= ~GSC_IRQ_FRMDONE_MASK;
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writel(cfg, dev->regs + GSC_IRQ);
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}
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void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask)
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{
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u32 cfg;
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cfg = readl(dev->regs + GSC_IRQ);
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if (mask)
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cfg |= GSC_IRQ_ENABLE;
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else
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cfg &= ~GSC_IRQ_ENABLE;
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writel(cfg, dev->regs + GSC_IRQ);
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}
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void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift,
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bool enable)
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{
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u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
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u32 mask = 1 << shift;
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cfg &= ~mask;
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cfg |= enable << shift;
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writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
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writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
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writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
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}
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void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift,
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bool enable)
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{
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u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
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u32 mask = 1 << shift;
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cfg &= ~mask;
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cfg |= enable << shift;
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writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
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writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
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writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
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}
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void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr,
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int index)
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{
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pr_debug("src_buf[%d]: %pad, cb: %pad, cr: %pad", index,
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&addr->y, &addr->cb, &addr->cr);
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writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index));
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writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index));
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writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index));
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}
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void gsc_hw_set_output_addr(struct gsc_dev *dev,
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struct gsc_addr *addr, int index)
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{
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pr_debug("dst_buf[%d]: %pad, cb: %pad, cr: %pad",
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index, &addr->y, &addr->cb, &addr->cr);
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writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index));
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writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index));
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writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index));
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}
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void gsc_hw_set_input_path(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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u32 cfg = readl(dev->regs + GSC_IN_CON);
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cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
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if (ctx->in_path == GSC_DMA)
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cfg |= GSC_IN_PATH_MEMORY;
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writel(cfg, dev->regs + GSC_IN_CON);
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}
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void gsc_hw_set_in_size(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->s_frame;
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u32 cfg;
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/* Set input pixel offset */
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cfg = GSC_SRCIMG_OFFSET_X(frame->crop.left);
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cfg |= GSC_SRCIMG_OFFSET_Y(frame->crop.top);
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writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
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/* Set input original size */
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cfg = GSC_SRCIMG_WIDTH(frame->f_width);
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cfg |= GSC_SRCIMG_HEIGHT(frame->f_height);
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writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
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/* Set input cropped size */
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cfg = GSC_CROPPED_WIDTH(frame->crop.width);
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cfg |= GSC_CROPPED_HEIGHT(frame->crop.height);
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writel(cfg, dev->regs + GSC_CROPPED_SIZE);
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}
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void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->s_frame;
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u32 cfg;
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cfg = readl(dev->regs + GSC_IN_CON);
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if (frame->colorspace == V4L2_COLORSPACE_REC709)
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cfg |= GSC_IN_RGB_HD_WIDE;
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else
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cfg |= GSC_IN_RGB_SD_WIDE;
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if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
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cfg |= GSC_IN_RGB565;
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else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
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cfg |= GSC_IN_XRGB8888;
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writel(cfg, dev->regs + GSC_IN_CON);
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}
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void gsc_hw_set_in_image_format(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->s_frame;
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u32 i, depth = 0;
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u32 cfg;
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cfg = readl(dev->regs + GSC_IN_CON);
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cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
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GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
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GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE);
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writel(cfg, dev->regs + GSC_IN_CON);
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if (is_rgb(frame->fmt->color)) {
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gsc_hw_set_in_image_rgb(ctx);
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return;
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}
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for (i = 0; i < frame->fmt->num_planes; i++)
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depth += frame->fmt->depth[i];
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switch (frame->fmt->num_comp) {
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case 1:
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cfg |= GSC_IN_YUV422_1P;
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if (frame->fmt->yorder == GSC_LSB_Y)
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cfg |= GSC_IN_YUV422_1P_ORDER_LSB_Y;
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else
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cfg |= GSC_IN_YUV422_1P_OEDER_LSB_C;
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if (frame->fmt->corder == GSC_CBCR)
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cfg |= GSC_IN_CHROMA_ORDER_CBCR;
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else
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cfg |= GSC_IN_CHROMA_ORDER_CRCB;
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break;
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case 2:
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if (depth == 12)
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cfg |= GSC_IN_YUV420_2P;
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else
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cfg |= GSC_IN_YUV422_2P;
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if (frame->fmt->corder == GSC_CBCR)
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cfg |= GSC_IN_CHROMA_ORDER_CBCR;
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else
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cfg |= GSC_IN_CHROMA_ORDER_CRCB;
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break;
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case 3:
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if (depth == 12)
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cfg |= GSC_IN_YUV420_3P;
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else
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cfg |= GSC_IN_YUV422_3P;
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break;
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}
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if (is_tiled(frame->fmt))
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cfg |= GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE;
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writel(cfg, dev->regs + GSC_IN_CON);
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}
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void gsc_hw_set_output_path(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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u32 cfg = readl(dev->regs + GSC_OUT_CON);
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cfg &= ~GSC_OUT_PATH_MASK;
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if (ctx->out_path == GSC_DMA)
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cfg |= GSC_OUT_PATH_MEMORY;
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else
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cfg |= GSC_OUT_PATH_LOCAL;
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writel(cfg, dev->regs + GSC_OUT_CON);
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}
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void gsc_hw_set_out_size(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->d_frame;
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u32 cfg;
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/* Set output original size */
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if (ctx->out_path == GSC_DMA) {
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cfg = GSC_DSTIMG_OFFSET_X(frame->crop.left);
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cfg |= GSC_DSTIMG_OFFSET_Y(frame->crop.top);
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writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
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cfg = GSC_DSTIMG_WIDTH(frame->f_width);
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cfg |= GSC_DSTIMG_HEIGHT(frame->f_height);
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writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
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}
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/* Set output scaled size */
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if (ctx->gsc_ctrls.rotate->val == 90 ||
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ctx->gsc_ctrls.rotate->val == 270) {
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cfg = GSC_SCALED_WIDTH(frame->crop.height);
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cfg |= GSC_SCALED_HEIGHT(frame->crop.width);
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} else {
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cfg = GSC_SCALED_WIDTH(frame->crop.width);
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cfg |= GSC_SCALED_HEIGHT(frame->crop.height);
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}
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writel(cfg, dev->regs + GSC_SCALED_SIZE);
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}
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void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->d_frame;
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u32 cfg;
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cfg = readl(dev->regs + GSC_OUT_CON);
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if (frame->colorspace == V4L2_COLORSPACE_REC709)
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cfg |= GSC_OUT_RGB_HD_WIDE;
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else
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cfg |= GSC_OUT_RGB_SD_WIDE;
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if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
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cfg |= GSC_OUT_RGB565;
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else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
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cfg |= GSC_OUT_XRGB8888;
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writel(cfg, dev->regs + GSC_OUT_CON);
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}
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void gsc_hw_set_out_image_format(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_frame *frame = &ctx->d_frame;
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u32 i, depth = 0;
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u32 cfg;
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cfg = readl(dev->regs + GSC_OUT_CON);
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cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
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GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
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GSC_OUT_TILE_TYPE_MASK | GSC_OUT_TILE_MODE);
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writel(cfg, dev->regs + GSC_OUT_CON);
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if (is_rgb(frame->fmt->color)) {
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gsc_hw_set_out_image_rgb(ctx);
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return;
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}
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if (ctx->out_path != GSC_DMA) {
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cfg |= GSC_OUT_YUV444;
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goto end_set;
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}
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for (i = 0; i < frame->fmt->num_planes; i++)
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depth += frame->fmt->depth[i];
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switch (frame->fmt->num_comp) {
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case 1:
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cfg |= GSC_OUT_YUV422_1P;
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if (frame->fmt->yorder == GSC_LSB_Y)
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cfg |= GSC_OUT_YUV422_1P_ORDER_LSB_Y;
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else
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cfg |= GSC_OUT_YUV422_1P_OEDER_LSB_C;
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if (frame->fmt->corder == GSC_CBCR)
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cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
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else
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cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
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break;
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case 2:
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if (depth == 12)
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cfg |= GSC_OUT_YUV420_2P;
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else
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cfg |= GSC_OUT_YUV422_2P;
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if (frame->fmt->corder == GSC_CBCR)
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cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
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else
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cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
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break;
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case 3:
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cfg |= GSC_OUT_YUV420_3P;
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break;
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}
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if (is_tiled(frame->fmt))
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cfg |= GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE;
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end_set:
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writel(cfg, dev->regs + GSC_OUT_CON);
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}
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void gsc_hw_set_prescaler(struct gsc_ctx *ctx)
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{
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struct gsc_dev *dev = ctx->gsc_dev;
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struct gsc_scaler *sc = &ctx->scaler;
|
||
|
|
u32 cfg;
|
||
|
|
|
||
|
|
cfg = GSC_PRESC_SHFACTOR(sc->pre_shfactor);
|
||
|
|
cfg |= GSC_PRESC_H_RATIO(sc->pre_hratio);
|
||
|
|
cfg |= GSC_PRESC_V_RATIO(sc->pre_vratio);
|
||
|
|
writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
|
||
|
|
}
|
||
|
|
|
||
|
|
void gsc_hw_set_mainscaler(struct gsc_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct gsc_dev *dev = ctx->gsc_dev;
|
||
|
|
struct gsc_scaler *sc = &ctx->scaler;
|
||
|
|
u32 cfg;
|
||
|
|
|
||
|
|
cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
|
||
|
|
writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
|
||
|
|
|
||
|
|
cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
|
||
|
|
writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
|
||
|
|
}
|
||
|
|
|
||
|
|
void gsc_hw_set_rotation(struct gsc_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct gsc_dev *dev = ctx->gsc_dev;
|
||
|
|
u32 cfg;
|
||
|
|
|
||
|
|
cfg = readl(dev->regs + GSC_IN_CON);
|
||
|
|
cfg &= ~GSC_IN_ROT_MASK;
|
||
|
|
|
||
|
|
switch (ctx->gsc_ctrls.rotate->val) {
|
||
|
|
case 270:
|
||
|
|
cfg |= GSC_IN_ROT_270;
|
||
|
|
break;
|
||
|
|
case 180:
|
||
|
|
cfg |= GSC_IN_ROT_180;
|
||
|
|
break;
|
||
|
|
case 90:
|
||
|
|
if (ctx->gsc_ctrls.hflip->val)
|
||
|
|
cfg |= GSC_IN_ROT_90_XFLIP;
|
||
|
|
else if (ctx->gsc_ctrls.vflip->val)
|
||
|
|
cfg |= GSC_IN_ROT_90_YFLIP;
|
||
|
|
else
|
||
|
|
cfg |= GSC_IN_ROT_90;
|
||
|
|
break;
|
||
|
|
case 0:
|
||
|
|
if (ctx->gsc_ctrls.hflip->val)
|
||
|
|
cfg |= GSC_IN_ROT_XFLIP;
|
||
|
|
else if (ctx->gsc_ctrls.vflip->val)
|
||
|
|
cfg |= GSC_IN_ROT_YFLIP;
|
||
|
|
}
|
||
|
|
|
||
|
|
writel(cfg, dev->regs + GSC_IN_CON);
|
||
|
|
}
|
||
|
|
|
||
|
|
void gsc_hw_set_global_alpha(struct gsc_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct gsc_dev *dev = ctx->gsc_dev;
|
||
|
|
struct gsc_frame *frame = &ctx->d_frame;
|
||
|
|
u32 cfg;
|
||
|
|
|
||
|
|
if (!is_rgb(frame->fmt->color)) {
|
||
|
|
pr_debug("Not a RGB format");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
cfg = readl(dev->regs + GSC_OUT_CON);
|
||
|
|
cfg &= ~GSC_OUT_GLOBAL_ALPHA_MASK;
|
||
|
|
|
||
|
|
cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val);
|
||
|
|
writel(cfg, dev->regs + GSC_OUT_CON);
|
||
|
|
}
|
||
|
|
|
||
|
|
void gsc_hw_set_sfr_update(struct gsc_ctx *ctx)
|
||
|
|
{
|
||
|
|
struct gsc_dev *dev = ctx->gsc_dev;
|
||
|
|
u32 cfg;
|
||
|
|
|
||
|
|
cfg = readl(dev->regs + GSC_ENABLE);
|
||
|
|
cfg |= GSC_ENABLE_SFR_UPDATE;
|
||
|
|
writel(cfg, dev->regs + GSC_ENABLE);
|
||
|
|
}
|