393 lines
9.4 KiB
C
393 lines
9.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _AUTOK_H_
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#define _AUTOK_H_
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/scatterlist.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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struct msdc_host;
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#define E_RES_PASS (0)
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#define E_RES_CMD_TMO (1<<0)
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#define E_RES_RSP_CRC (1<<1)
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#define E_RES_DAT_CRC (1<<2)
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#define E_RES_DAT_TMO (1<<3)
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#define E_RES_W_CRC (1<<4)
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#define E_RES_ERR (1<<5)
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#define E_RES_START (1<<6)
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#define E_RES_PW_SMALL (1<<7)
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#define E_RES_KEEP_OLD (1<<8)
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#define E_RES_CMP_ERR (1<<9)
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#define E_RES_FATAL_ERR (1<<10)
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#define E_RESULT_MAX
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#define MERGE_CMD (1<<0)
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#define MERGE_DAT (1<<1)
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#define MERGE_DS_DAT (1<<2)
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#define MERGE_DS_CMD (1<<3)
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#define MERGE_DEVICE_D_RX (1<<4)
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#define MERGE_DEVICE_C_RX (1<<5)
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#define MERGE_HOST_D_TX (1<<6)
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#define MERGE_HOST_C_TX (1<<7)
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#define MERGE_HOST_CLK_TX (1<<8)
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#define MERGE_HS200_SDR104 (MERGE_CMD | MERGE_DAT)
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#define MERGE_HS400 (MERGE_CMD | MERGE_DS_DAT)
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#define MERGE_DDR208 (MERGE_CMD \
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| MERGE_DS_DAT \
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| MERGE_DEVICE_D_RX \
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| MERGE_HOST_D_TX)
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#ifndef NULL
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#define NULL 0
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#endif
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#ifndef TRUE
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#define TRUE (0 == 0)
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#endif
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#ifndef FALSE
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#define FALSE (0 != 0)
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#endif
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#define AUTOK_DBG_OFF 0
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#define AUTOK_DBG_ERROR 1
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#define AUTOK_DBG_RES 2
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#define AUTOK_DBG_WARN 3
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#define AUTOK_DBG_TRACE 4
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#define AUTOK_DBG_LOUD 5
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extern unsigned int autok_debug_level;
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#define AUTOK_DBGPRINT(_level, _fmt ...) \
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({ \
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if (autok_debug_level >= _level) { \
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pr_info(_fmt); \
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} \
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})
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#define AUTOK_RAWPRINT(_fmt ...) \
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({ \
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pr_info(_fmt); \
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})
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enum ERROR_TYPE {
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CMD_ERROR = 0,
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DATA_ERROR,
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CRC_STATUS_ERROR,
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};
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enum TUNE_TX_TYPE {
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TX_CMD = 0,
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TX_DATA,
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};
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enum AUTOK_PARAM {
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/* command response sample selection
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* (MSDC_SMPL_RISING, MSDC_SMPL_FALLING)
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*/
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CMD_EDGE,
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/* cmd response async fifo out edge select */
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CMD_FIFO_EDGE,
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/* read data sample selection
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* (MSDC_SMPL_RISING, MSDC_SMPL_FALLING)
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*/
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RDATA_EDGE,
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/* read data async fifo out edge select */
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RD_FIFO_EDGE,
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/* write data crc status async fifo out edge select */
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WD_FIFO_EDGE,
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/* [Data Tune]CMD Pad RX Delay Line1 Control.
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* This register is used to
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* fine-tune CMD pad macro respose latch timing.
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* Total 32 stages[Data Tune]
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*/
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CMD_RD_D_DLY1,
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/* [Data Tune]CMD Pad RX Delay Line1 Sel-> delay cell1 enable */
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CMD_RD_D_DLY1_SEL,
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/* [Data Tune]CMD Pad RX Delay Line2 Control. This register is used to
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* fine-tune CMD pad macro respose latch timing.
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* Total 32 stages[Data Tune]
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*/
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CMD_RD_D_DLY2,
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/* [Data Tune]CMD Pad RX Delay Line1 Sel-> delay cell2 enable */
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CMD_RD_D_DLY2_SEL,
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/* [Data Tune]DAT Pad RX Delay Line1 Control (for MSDC RD),
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* Total 32 stages [Data Tune]
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*/
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DAT_RD_D_DLY1,
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/* [Data Tune]DAT Pad RX Delay Line1 Sel-> delay cell1 enable */
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DAT_RD_D_DLY1_SEL,
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/* [Data Tune]DAT Pad RX Delay Line2 Control (for MSDC RD),
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* Total 32 stages [Data Tune]
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*/
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DAT_RD_D_DLY2,
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/* [Data Tune]DAT Pad RX Delay Line2 Sel-> delay cell2 enable */
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DAT_RD_D_DLY2_SEL,
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/* Internal MSDC clock phase selection. Total 8 stages,
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* each stage can delay 1 clock period of msdc_src_ck
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*/
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INT_DAT_LATCH_CK,
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/* DS Pad Z clk delay count, range: 0~63, Z dly1(0~31)+Z dly2(0~31) */
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EMMC50_DS_Z_DLY1,
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/* DS Pad Z clk del sel: [dly2_sel:dly1_sel] -> [0,1]:
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* dly1 enable [1,2]:dl2 & dly1 enable ,else :no dly enable
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*/
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EMMC50_DS_Z_DLY1_SEL,
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/* DS Pad Z clk delay count, range: 0~63, Z dly1(0~31)+Z dly2(0~31) */
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EMMC50_DS_Z_DLY2,
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/* DS Pad Z clk del sel: [dly2_sel:dly1_sel] -> [0,1]:
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* dly1 enable [1,2]:dl2 & dly1 enable ,else :no dly enable,
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*/
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EMMC50_DS_Z_DLY2_SEL,
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/* DS Pad Z_DLY clk delay count, range: 0~31 */
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EMMC50_DS_ZDLY_DLY,
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/* eMMC50 CMD TX dly */
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EMMC50_CMD_TX_DLY,
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/* eMMC50 DATA TX dly */
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EMMC50_DATA0_TX_DLY,
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EMMC50_DATA1_TX_DLY,
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EMMC50_DATA2_TX_DLY,
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EMMC50_DATA3_TX_DLY,
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EMMC50_DATA4_TX_DLY,
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EMMC50_DATA5_TX_DLY,
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EMMC50_DATA6_TX_DLY,
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EMMC50_DATA7_TX_DLY,
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/* CLK Pad TX Delay Control. This register is used to
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* add delay to CLK phase. Total 32 stages
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*/
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PAD_CLK_TXDLY_AUTOK,
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TUNING_PARAM_COUNT,
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/* CMD scan result */
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CMD_SCAN_R0,
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CMD_SCAN_R1,
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CMD_SCAN_R2,
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CMD_SCAN_R3,
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CMD_SCAN_R4,
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CMD_SCAN_R5,
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CMD_SCAN_R6,
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CMD_SCAN_R7,
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CMD_SCAN_F0,
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CMD_SCAN_F1,
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CMD_SCAN_F2,
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CMD_SCAN_F3,
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CMD_SCAN_F4,
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CMD_SCAN_F5,
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CMD_SCAN_F6,
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CMD_SCAN_F7,
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/* DATA scan result */
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DAT_SCAN_R0,
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DAT_SCAN_R1,
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DAT_SCAN_R2,
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DAT_SCAN_R3,
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DAT_SCAN_R4,
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DAT_SCAN_R5,
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DAT_SCAN_R6,
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DAT_SCAN_R7,
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DAT_SCAN_F0,
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DAT_SCAN_F1,
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DAT_SCAN_F2,
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DAT_SCAN_F3,
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DAT_SCAN_F4,
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DAT_SCAN_F5,
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DAT_SCAN_F6,
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DAT_SCAN_F7,
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/* DS CMD scan result */
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DS_CMD_SCAN_0,
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DS_CMD_SCAN_1,
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DS_CMD_SCAN_2,
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DS_CMD_SCAN_3,
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DS_CMD_SCAN_4,
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DS_CMD_SCAN_5,
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DS_CMD_SCAN_6,
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DS_CMD_SCAN_7,
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/* DS DAT scan result */
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DS_DAT_SCAN_0,
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DS_DAT_SCAN_1,
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DS_DAT_SCAN_2,
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DS_DAT_SCAN_3,
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DS_DAT_SCAN_4,
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DS_DAT_SCAN_5,
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DS_DAT_SCAN_6,
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DS_DAT_SCAN_7,
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/* Device CMD RX result */
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D_CMD_SCAN_0,
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D_CMD_SCAN_1,
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D_CMD_SCAN_2,
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D_CMD_SCAN_3,
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/* Device DATA RX result */
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D_DATA_SCAN_0,
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D_DATA_SCAN_1,
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D_DATA_SCAN_2,
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D_DATA_SCAN_3,
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/* Host CMD TX result */
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H_CMD_SCAN_0,
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H_CMD_SCAN_1,
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H_CMD_SCAN_2,
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H_CMD_SCAN_3,
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/* Host DATA TX result */
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H_DATA_SCAN_0,
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H_DATA_SCAN_1,
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H_DATA_SCAN_2,
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H_DATA_SCAN_3,
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/* AUTOK version */
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AUTOK_VER0,
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AUTOK_VER1,
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AUTOK_VER2,
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AUTOK_VER3,
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CMD_MAX_WIN,
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DAT_MAX_WIN,
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DS_MAX_WIN,
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DEV_D_RX_MAX_WIN,
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DEV_C_RX_MAX_WIN,
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H_D_TX_MAX_WIN,
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H_C_TX_MAX_WIN,
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H_CLK_TX_MAX_WIN,
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TUNING_PARA_SCAN_COUNT,
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/* Data line rising/falling latch
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* fine tune selection in read transaction.
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* 1'b0: All data line share one value indicated
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* by MSDC_IOCON.R_D_SMPL.
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* 1'b1: Each data line has its own selection value indicated by
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* Data line (x): MSDC_IOCON.R_D(x)_SMPL
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*/
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READ_DATA_SMPL_SEL,
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/* Data line rising/falling latch
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* fine tune selection in write transaction.
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* 1'b0: All data line share one value indicated by
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* MSDC_IOCON.W_D_SMPL.
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* 1'b1: Each data line has its own selection value
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* indicated by Data line (x): MSDC_IOCON.W_D(x)_SMPL
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*/
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WRITE_DATA_SMPL_SEL,
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/* Data line delay line fine tune selection.
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*1'b0: All data line share one delay
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* selection value indicated by PAD_TUNE.PAD_DAT_RD_RXDLY.
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* 1'b1: Each data line has its
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* own delay selection value indicated by
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* Data line (x): DAT_RD_DLY(x).DAT0_RD_DLY
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*/
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DATA_DLYLINE_SEL,
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/* [Data Tune]CMD & DATA Pin tune Data Selection[Data Tune Sel] */
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MSDC_DAT_TUNE_SEL,
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/* [Async_FIFO Mode Sel For Write Path] */
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MSDC_WCRC_ASYNC_FIFO_SEL,
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/* [Async_FIFO Mode Sel For CMD Path] */
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MSDC_RESP_ASYNC_FIFO_SEL,
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/* Write Path Mux for emmc50 function & emmc45 function ,
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* Only emmc50 design valid,[1-eMMC50, 0-eMMC45]
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*/
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EMMC50_WDATA_MUX_EN,
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/* CMD Path Mux for emmc50 function & emmc45 function ,
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* Only emmc50 design valid,[1-eMMC50, 0-eMMC45]
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*/
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EMMC50_CMD_MUX_EN,
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/* CMD response DS latch or internal clk latch */
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EMMC50_CMD_RESP_LATCH,
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/* write data crc status async fifo output edge select */
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EMMC50_WDATA_EDGE,
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/* CKBUF in CKGEN Delay Selection. Total 32 stages */
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CKGEN_MSDC_DLY_SEL,
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/* CMD response turn around period.
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*The turn around cycle = CMD_RSP_TA_CNTR + 2,
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* Only for USH104 mode, this register should be
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* set to 0 in non-UHS104 mode
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*/
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CMD_RSP_TA_CNTR,
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/* Write data and CRC status turn around period.
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* The turn around cycle = WRDAT_CRCS_TA_CNTR + 2,
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* Only for USH104 mode, this register should be set to 0
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* in non-UHS104 mode
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*/
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WRDAT_CRCS_TA_CNTR,
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SDC_RX_ENHANCE,
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TOTAL_PARAM_COUNT
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};
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/**********************************************************
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* Function Declaration *
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**********************************************************/
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extern int autok_path_sel(struct msdc_host *host);
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extern int autok_init_ddr208(struct msdc_host *host);
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extern int autok_init_sdr104(struct msdc_host *host);
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extern int autok_init_hs200(struct msdc_host *host);
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extern int autok_init_hs400(struct msdc_host *host);
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extern int autok_offline_tuning_clk_TX(struct msdc_host *host,
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unsigned int opcode);
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extern int autok_offline_tuning_TX(struct msdc_host *host, u8 *res);
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extern int autok_offline_tuning_device_RX(struct msdc_host *host, u8 *res);
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extern void autok_msdc_tx_setting(struct msdc_host *host, struct mmc_ios *ios);
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extern void autok_low_speed_switch_edge(struct msdc_host *host,
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struct mmc_ios *ios, enum ERROR_TYPE error_type);
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extern void autok_tuning_parameter_init(struct msdc_host *host, u8 *res);
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extern int autok_sdio30_plus_tuning(struct msdc_host *host, u8 *res);
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extern int autok_execute_tuning(struct msdc_host *host, u8 *res);
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extern int hs200_execute_tuning(struct msdc_host *host, u8 *res);
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extern int hs200_execute_tuning_cmd(struct msdc_host *host, u8 *res);
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extern int hs400_execute_tuning(struct msdc_host *host, u8 *res);
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extern int hs400_execute_tuning_cmd(struct msdc_host *host, u8 *res);
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extern int autok_vcore_merge_sel(struct msdc_host *host,
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unsigned int merge_cap);
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#endif /* _AUTOK_H_ */
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