342 lines
7.5 KiB
C
342 lines
7.5 KiB
C
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/*
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/mtd/rawnand.h>
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#define ONFI_DYN_TIMING_MAX U16_MAX
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static const struct nand_data_interface onfi_sdr_timings[] = {
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/* Mode 0 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 20000,
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.tALS_min = 50000,
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.tAR_min = 25000,
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.tCEA_max = 100000,
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.tCEH_min = 20000,
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.tCH_min = 20000,
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.tCHZ_max = 100000,
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.tCLH_min = 20000,
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.tCLR_min = 20000,
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.tCLS_min = 50000,
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.tCOH_min = 0,
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.tCS_min = 70000,
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.tDH_min = 20000,
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.tDS_min = 40000,
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.tFEAT_max = 1000000,
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.tIR_min = 10000,
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.tITC_max = 1000000,
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.tRC_min = 100000,
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.tREA_max = 40000,
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.tREH_min = 30000,
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.tRHOH_min = 0,
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.tRHW_min = 200000,
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.tRHZ_max = 200000,
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.tRLOH_min = 0,
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.tRP_min = 50000,
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.tRR_min = 40000,
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.tRST_max = 250000000000ULL,
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.tWB_max = 200000,
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.tWC_min = 100000,
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.tWH_min = 30000,
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.tWHR_min = 120000,
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.tWP_min = 50000,
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.tWW_min = 100000,
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},
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},
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/* Mode 1 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 25000,
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.tAR_min = 10000,
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.tCEA_max = 45000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 25000,
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.tCOH_min = 15000,
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.tCS_min = 35000,
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.tDH_min = 10000,
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.tDS_min = 20000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 50000,
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.tREA_max = 30000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 25000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 45000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 25000,
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.tWW_min = 100000,
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},
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},
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/* Mode 2 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 15000,
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.tAR_min = 10000,
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.tCEA_max = 30000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 15000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 15000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 35000,
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.tREA_max = 25000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tRP_min = 17000,
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.tWC_min = 35000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 17000,
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.tWW_min = 100000,
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},
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},
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/* Mode 3 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 50000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 30000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 15000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 30000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 15000,
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.tWW_min = 100000,
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},
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},
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/* Mode 4 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 20000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 25000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 12000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 25000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 12000,
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.tWW_min = 100000,
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},
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},
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/* Mode 5 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 15000,
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.tDH_min = 5000,
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.tDS_min = 7000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 20000,
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.tREA_max = 16000,
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.tREH_min = 7000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 10000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 20000,
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.tWH_min = 7000,
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.tWHR_min = 80000,
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.tWP_min = 10000,
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.tWW_min = 100000,
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},
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},
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};
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/**
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* onfi_async_timing_mode_to_sdr_timings - [NAND Interface] Retrieve NAND
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* timings according to the given ONFI timing mode
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* @mode: ONFI timing mode
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*/
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const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
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{
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if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
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return ERR_PTR(-EINVAL);
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return &onfi_sdr_timings[mode].timings.sdr;
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}
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EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
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/**
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* onfi_fill_data_interface - [NAND Interface] Initialize a data interface from
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* given ONFI mode
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* @mode: The ONFI timing mode
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*/
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int onfi_fill_data_interface(struct nand_chip *chip,
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enum nand_data_interface_type type,
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int timing_mode)
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{
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struct nand_data_interface *iface = &chip->data_interface;
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struct onfi_params *onfi = chip->parameters.onfi;
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if (type != NAND_SDR_IFACE)
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return -EINVAL;
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if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
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return -EINVAL;
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*iface = onfi_sdr_timings[timing_mode];
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/*
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* Initialize timings that cannot be deduced from timing mode:
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* tPROG, tBERS, tR and tCCS.
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* These information are part of the ONFI parameter page.
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*/
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if (onfi) {
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struct nand_sdr_timings *timings = &iface->timings.sdr;
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/* microseconds -> picoseconds */
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timings->tPROG_max = 1000000ULL * onfi->tPROG;
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timings->tBERS_max = 1000000ULL * onfi->tBERS;
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timings->tR_max = 1000000ULL * onfi->tR;
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/* nanoseconds -> picoseconds */
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timings->tCCS_min = 1000UL * onfi->tCCS;
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} else {
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struct nand_sdr_timings *timings = &iface->timings.sdr;
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/*
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* For non-ONFI chips we use the highest possible value for
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* tPROG and tBERS. tR and tCCS will take the default values
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* precised in the ONFI specification for timing mode 0,
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* respectively 200us and 500ns.
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*/
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/* microseconds -> picoseconds */
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timings->tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
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timings->tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
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timings->tR_max = 200000000;
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timings->tCCS_min = 500000;
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}
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return 0;
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}
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EXPORT_SYMBOL(onfi_fill_data_interface);
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