436 lines
12 KiB
C
436 lines
12 KiB
C
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/*
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* dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
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*
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* Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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* Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/stmmac.h>
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#include <linux/phy.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include "stmmac_platform.h"
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#define DWMAC_125MHZ 125000000
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#define DWMAC_50MHZ 50000000
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#define DWMAC_25MHZ 25000000
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#define DWMAC_2_5MHZ 2500000
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#define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
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iface == PHY_INTERFACE_MODE_RGMII_ID || \
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iface == PHY_INTERFACE_MODE_RGMII_RXID || \
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iface == PHY_INTERFACE_MODE_RGMII_TXID)
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#define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
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iface == PHY_INTERFACE_MODE_GMII)
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/* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families)
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*
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* Below table summarizes the clock requirement and clock sources for
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* supported phy interface modes with link speeds.
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* ________________________________________________
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*| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
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* ------------------------------------------------
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*| MII | n/a | 25Mhz |
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*| | | txclk |
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* ------------------------------------------------
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*| GMII | 125Mhz | 25Mhz |
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*| | clk-125/txclk | txclk |
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* ------------------------------------------------
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*| RGMII | 125Mhz | 25Mhz |
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*| | clk-125/txclk | clkgen |
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*| | clkgen | |
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* ------------------------------------------------
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*| RMII | n/a | 25Mhz |
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*| | |clkgen/phyclk-in |
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* ------------------------------------------------
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*
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* Register Configuration
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*-------------------------------
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* src |BIT(8)| BIT(7)| BIT(6)|
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*-------------------------------
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* txclk | 0 | n/a | 1 |
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*-------------------------------
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* ck_125| 0 | n/a | 0 |
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*-------------------------------
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* phyclk| 1 | 0 | n/a |
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*-------------------------------
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* clkgen| 1 | 1 | n/a |
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*-------------------------------
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*/
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#define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6)
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#define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8)
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#define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
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#define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
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/* STiD127 register definitions
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*-----------------------
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* src |BIT(6)| BIT(7)|
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*-----------------------
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* MII | 1 | n/a |
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*-----------------------
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* RMII | n/a | 1 |
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* clkgen| | |
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*-----------------------
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* RMII | n/a | 0 |
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* phyclk| | |
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*-----------------------
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* RGMII | 1 | n/a |
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* clkgen| | |
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*-----------------------
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*/
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#define STID127_RETIME_SRC_MASK GENMASK(7, 6)
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#define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
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#define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6)
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#define ENMII_MASK GENMASK(5, 5)
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#define ENMII BIT(5)
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#define EN_MASK GENMASK(1, 1)
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#define EN BIT(1)
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/*
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* 3 bits [4:2]
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* 000-GMII/MII
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* 001-RGMII
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* 010-SGMII
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* 100-RMII
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*/
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#define MII_PHY_SEL_MASK GENMASK(4, 2)
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#define ETH_PHY_SEL_RMII BIT(4)
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#define ETH_PHY_SEL_SGMII BIT(3)
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#define ETH_PHY_SEL_RGMII BIT(2)
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#define ETH_PHY_SEL_GMII 0x0
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#define ETH_PHY_SEL_MII 0x0
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struct sti_dwmac {
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int interface; /* MII interface */
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bool ext_phyclk; /* Clock from external PHY */
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u32 tx_retime_src; /* TXCLK Retiming*/
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struct clk *clk; /* PHY clock */
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u32 ctrl_reg; /* GMAC glue-logic control register */
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int clk_sel_reg; /* GMAC ext clk selection register */
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struct regmap *regmap;
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bool gmac_en;
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u32 speed;
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void (*fix_retime_src)(void *priv, unsigned int speed);
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};
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struct sti_dwmac_of_data {
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void (*fix_retime_src)(void *priv, unsigned int speed);
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};
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static u32 phy_intf_sels[] = {
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[PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
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[PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
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[PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
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[PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
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[PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
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[PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
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};
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enum {
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TX_RETIME_SRC_NA = 0,
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TX_RETIME_SRC_TXCLK = 1,
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TX_RETIME_SRC_CLK_125,
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TX_RETIME_SRC_PHYCLK,
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TX_RETIME_SRC_CLKGEN,
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};
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static u32 stih4xx_tx_retime_val[] = {
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[TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125,
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[TX_RETIME_SRC_CLK_125] = 0x0,
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[TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK,
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[TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK
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| STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
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};
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static void stih4xx_fix_retime_src(void *priv, u32 spd)
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{
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struct sti_dwmac *dwmac = priv;
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u32 src = dwmac->tx_retime_src;
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u32 reg = dwmac->ctrl_reg;
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u32 freq = 0;
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if (dwmac->interface == PHY_INTERFACE_MODE_MII) {
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src = TX_RETIME_SRC_TXCLK;
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} else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
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if (dwmac->ext_phyclk) {
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src = TX_RETIME_SRC_PHYCLK;
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} else {
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src = TX_RETIME_SRC_CLKGEN;
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freq = DWMAC_50MHZ;
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}
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} else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
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/* On GiGa clk source can be either ext or from clkgen */
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if (spd == SPEED_1000) {
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freq = DWMAC_125MHZ;
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} else {
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/* Switch to clkgen for these speeds */
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src = TX_RETIME_SRC_CLKGEN;
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if (spd == SPEED_100)
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freq = DWMAC_25MHZ;
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else if (spd == SPEED_10)
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freq = DWMAC_2_5MHZ;
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}
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}
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if (src == TX_RETIME_SRC_CLKGEN && freq)
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clk_set_rate(dwmac->clk, freq);
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regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK,
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stih4xx_tx_retime_val[src]);
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}
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static void stid127_fix_retime_src(void *priv, u32 spd)
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{
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struct sti_dwmac *dwmac = priv;
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u32 reg = dwmac->ctrl_reg;
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u32 freq = 0;
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u32 val = 0;
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if (dwmac->interface == PHY_INTERFACE_MODE_MII) {
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val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK;
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} else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
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if (!dwmac->ext_phyclk) {
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val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK;
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freq = DWMAC_50MHZ;
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}
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} else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
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val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK;
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if (spd == SPEED_1000)
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freq = DWMAC_125MHZ;
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else if (spd == SPEED_100)
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freq = DWMAC_25MHZ;
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else if (spd == SPEED_10)
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freq = DWMAC_2_5MHZ;
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}
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if (freq)
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clk_set_rate(dwmac->clk, freq);
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regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val);
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}
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static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)
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{
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struct regmap *regmap = dwmac->regmap;
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int iface = dwmac->interface;
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u32 reg = dwmac->ctrl_reg;
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u32 val;
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if (dwmac->gmac_en)
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regmap_update_bits(regmap, reg, EN_MASK, EN);
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regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
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val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
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regmap_update_bits(regmap, reg, ENMII_MASK, val);
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dwmac->fix_retime_src(dwmac, dwmac->speed);
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return 0;
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}
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static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
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struct platform_device *pdev)
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{
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct regmap *regmap;
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int err;
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/* clk selection from extra syscfg register */
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dwmac->clk_sel_reg = -ENXIO;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
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if (res)
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dwmac->clk_sel_reg = res->start;
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regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
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if (err) {
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dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
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return err;
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}
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dwmac->interface = of_get_phy_mode(np);
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dwmac->regmap = regmap;
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dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en");
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dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
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dwmac->tx_retime_src = TX_RETIME_SRC_NA;
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dwmac->speed = SPEED_100;
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if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
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const char *rs;
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dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN;
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err = of_property_read_string(np, "st,tx-retime-src", &rs);
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if (err < 0) {
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dev_warn(dev, "Use internal clock source\n");
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} else {
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if (!strcasecmp(rs, "clk_125"))
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dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125;
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else if (!strcasecmp(rs, "txclk"))
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dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK;
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}
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dwmac->speed = SPEED_1000;
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}
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dwmac->clk = devm_clk_get(dev, "sti-ethclk");
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if (IS_ERR(dwmac->clk)) {
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dev_warn(dev, "No phy clock provided...\n");
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dwmac->clk = NULL;
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}
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return 0;
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}
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static int sti_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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const struct sti_dwmac_of_data *data;
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struct stmmac_resources stmmac_res;
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struct sti_dwmac *dwmac;
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int ret;
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data = of_device_get_match_data(&pdev->dev);
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if (!data) {
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dev_err(&pdev->dev, "No OF match data provided\n");
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return -EINVAL;
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}
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac) {
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ret = -ENOMEM;
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goto err_remove_config_dt;
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}
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ret = sti_dwmac_parse_data(dwmac, pdev);
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if (ret) {
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dev_err(&pdev->dev, "Unable to parse OF data\n");
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goto err_remove_config_dt;
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}
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dwmac->fix_retime_src = data->fix_retime_src;
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plat_dat->bsp_priv = dwmac;
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plat_dat->fix_mac_speed = data->fix_retime_src;
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|
ret = clk_prepare_enable(dwmac->clk);
|
||
|
|
if (ret)
|
||
|
|
goto err_remove_config_dt;
|
||
|
|
|
||
|
|
ret = sti_dwmac_set_mode(dwmac);
|
||
|
|
if (ret)
|
||
|
|
goto disable_clk;
|
||
|
|
|
||
|
|
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
||
|
|
if (ret)
|
||
|
|
goto disable_clk;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
disable_clk:
|
||
|
|
clk_disable_unprepare(dwmac->clk);
|
||
|
|
err_remove_config_dt:
|
||
|
|
stmmac_remove_config_dt(pdev, plat_dat);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sti_dwmac_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
|
||
|
|
int ret = stmmac_dvr_remove(&pdev->dev);
|
||
|
|
|
||
|
|
clk_disable_unprepare(dwmac->clk);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM_SLEEP
|
||
|
|
static int sti_dwmac_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
|
||
|
|
int ret = stmmac_suspend(dev);
|
||
|
|
|
||
|
|
clk_disable_unprepare(dwmac->clk);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sti_dwmac_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
|
||
|
|
|
||
|
|
clk_prepare_enable(dwmac->clk);
|
||
|
|
sti_dwmac_set_mode(dwmac);
|
||
|
|
|
||
|
|
return stmmac_resume(dev);
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_PM_SLEEP */
|
||
|
|
|
||
|
|
static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend,
|
||
|
|
sti_dwmac_resume);
|
||
|
|
|
||
|
|
static const struct sti_dwmac_of_data stih4xx_dwmac_data = {
|
||
|
|
.fix_retime_src = stih4xx_fix_retime_src,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct sti_dwmac_of_data stid127_dwmac_data = {
|
||
|
|
.fix_retime_src = stid127_fix_retime_src,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id sti_dwmac_match[] = {
|
||
|
|
{ .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data},
|
||
|
|
{ .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data},
|
||
|
|
{ .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data},
|
||
|
|
{ .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data},
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, sti_dwmac_match);
|
||
|
|
|
||
|
|
static struct platform_driver sti_dwmac_driver = {
|
||
|
|
.probe = sti_dwmac_probe,
|
||
|
|
.remove = sti_dwmac_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "sti-dwmac",
|
||
|
|
.pm = &sti_dwmac_pm_ops,
|
||
|
|
.of_match_table = sti_dwmac_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(sti_dwmac_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
|
||
|
|
MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer");
|
||
|
|
MODULE_LICENSE("GPL");
|