214 lines
6.4 KiB
C
214 lines
6.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MT753X_H_
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#define _MT753X_H_
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/netdevice.h>
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#include <linux/of_mdio.h>
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#include <linux/workqueue.h>
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#include <linux/gpio/consumer.h>
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#ifdef CONFIG_SWCONFIG
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#include <linux/switch.h>
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#endif
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#include "mt753x_vlan.h"
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#define MT753X_DFL_CPU_PORT 6
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#define MT753X_NUM_PHYS 5
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#define MT753X_DFL_SMI_ADDR 0x1f
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#define MT753X_SMI_ADDR_MASK 0x1f
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struct gsw_mt753x;
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enum mt753x_model {
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MT7530 = 0x7530,
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MT7531 = 0x7531
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};
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struct mt753x_port_cfg {
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struct device_node *np;
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int phy_mode;
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u32 enabled: 1;
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u32 force_link: 1;
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u32 speed: 2;
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u32 duplex: 1;
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};
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struct mt753x_phy {
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struct gsw_mt753x *gsw;
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struct net_device netdev;
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struct phy_device *phydev;
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};
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struct gsw_mt753x {
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u32 id;
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struct device *dev;
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struct mii_bus *host_bus;
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struct mii_bus *gphy_bus;
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struct mutex mii_lock; /* MII access lock */
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u32 smi_addr;
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u32 phy_base;
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int direct_phy_access;
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enum mt753x_model model;
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const char *name;
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struct mt753x_port_cfg port5_cfg;
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struct mt753x_port_cfg port6_cfg;
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int phy_status_poll;
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struct mt753x_phy phys[MT753X_NUM_PHYS];
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int phy_link_sts;
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int irq;
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int reset_pin;
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struct work_struct irq_worker;
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#ifdef CONFIG_SWCONFIG
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struct switch_dev swdev;
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u32 cpu_port;
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#endif
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int global_vlan_enable;
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struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS];
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struct mt753x_port_entry port_entries[MT753X_NUM_PORTS];
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int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg);
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void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
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int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
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void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
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u16 val);
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struct list_head list;
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};
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struct chip_rev {
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const char *name;
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u32 rev;
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};
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struct mt753x_sw_id {
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enum mt753x_model model;
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int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev);
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int (*init)(struct gsw_mt753x *gsw);
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int (*post_init)(struct gsw_mt753x *gsw);
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};
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extern struct list_head mt753x_devs;
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struct gsw_mt753x *mt753x_get_gsw(u32 id);
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struct gsw_mt753x *mt753x_get_first_gsw(void);
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void mt753x_put_gsw(void);
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void mt753x_lock_gsw(void);
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u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg);
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void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val);
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int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg);
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void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
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int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
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void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
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u16 val);
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int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
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void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
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u16 val);
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void mt753x_irq_worker(struct work_struct *work);
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void mt753x_irq_enable(struct gsw_mt753x *gsw);
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/* MDIO Indirect Access Registers */
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#define MII_MMD_ACC_CTL_REG 0x0d
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#define MMD_CMD_S 14
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#define MMD_CMD_M 0xc000
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#define MMD_DEVAD_S 0
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#define MMD_DEVAD_M 0x1f
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/* MMD_CMD: MMD commands */
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#define MMD_ADDR 0
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#define MMD_DATA 1
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#define MII_MMD_ADDR_DATA_REG 0x0e
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/* Procedure of MT753x Internal Register Access
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*
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* 1. Internal Register Address
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*
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* The MT753x has a 16-bit register address and each register is 32-bit.
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* This means the lowest two bits are not used as the register address is
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* 4-byte aligned.
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*
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* Rest of the valid bits are divided into two parts:
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* Bit 15..6 is the Page address
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* Bit 5..2 is the low address
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*
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* -------------------------------------------------------------------
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* | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
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* |----------------------------------------|---------------|--------|
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* | Page Address | Address | Unused |
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* -------------------------------------------------------------------
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*
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* 2. MDIO access timing
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*
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* The MT753x uses the following MDIO timing for a single register read
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*
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* Phase 1: Write Page Address
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* -------------------------------------------------------------------
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* | ST | OP | PHY_ADDR | TYPE | RSVD | TA | RSVD | PAGE_ADDR |
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* -------------------------------------------------------------------
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* | 01 | 01 | 11111 | 1 | 1111 | xx | 00000 | REG_ADDR[15..6] |
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* -------------------------------------------------------------------
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*
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* Phase 2: Write low Address & Read low word
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* -------------------------------------------------------------------
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* | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA |
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* -------------------------------------------------------------------
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* | 01 | 10 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] |
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* -------------------------------------------------------------------
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*
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* Phase 3: Read high word
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* -------------------------------------------------------------------
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* | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA |
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* -------------------------------------------------------------------
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* | 01 | 10 | 11111 | 1 | 0000 | xx | DATA[31..16] |
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* -------------------------------------------------------------------
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*
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* The MT753x uses the following MDIO timing for a single register write
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*
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* Phase 1: Write Page Address (The same as read)
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*
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* Phase 2: Write low Address and low word
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* -------------------------------------------------------------------
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* | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA |
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* -------------------------------------------------------------------
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* | 01 | 01 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] |
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* -------------------------------------------------------------------
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*
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* Phase 3: write high word
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* -------------------------------------------------------------------
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* | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA |
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* -------------------------------------------------------------------
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* | 01 | 01 | 11111 | 1 | 0000 | xx | DATA[31..16] |
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* -------------------------------------------------------------------
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*
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*/
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/* Internal Register Address fields */
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#define MT753X_REG_PAGE_ADDR_S 6
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#define MT753X_REG_PAGE_ADDR_M 0xffc0
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#define MT753X_REG_ADDR_S 2
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#define MT753X_REG_ADDR_M 0x3c
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#endif /* _MT753X_H_ */
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