243 lines
6.5 KiB
C
243 lines
6.5 KiB
C
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/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2015,2017 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BMI_H_
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#define _BMI_H_
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#include "core.h"
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/*
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* Bootloader Messaging Interface (BMI)
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*
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* BMI is a very simple messaging interface used during initialization
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* to read memory, write memory, execute code, and to define an
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* application entry PC.
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*
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* It is used to download an application to QCA988x, to provide
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* patches to code that is already resident on QCA988x, and generally
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* to examine and modify state. The Host has an opportunity to use
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* BMI only once during bootup. Once the Host issues a BMI_DONE
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* command, this opportunity ends.
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*
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* The Host writes BMI requests to mailbox0, and reads BMI responses
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* from mailbox0. BMI requests all begin with a command
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* (see below for specific commands), and are followed by
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* command-specific data.
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*
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* Flow control:
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* The Host can only issue a command once the Target gives it a
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* "BMI Command Credit", using AR8K Counter #4. As soon as the
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* Target has completed a command, it issues another BMI Command
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* Credit (so the Host can issue the next command).
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*
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* BMI handles all required Target-side cache flushing.
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*/
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/* Maximum data size used for BMI transfers */
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#define BMI_MAX_DATA_SIZE 256
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/* len = cmd + addr + length */
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#define BMI_MAX_CMDBUF_SIZE (BMI_MAX_DATA_SIZE + \
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sizeof(u32) + \
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sizeof(u32) + \
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sizeof(u32))
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/* BMI Commands */
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enum bmi_cmd_id {
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BMI_NO_COMMAND = 0,
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BMI_DONE = 1,
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BMI_READ_MEMORY = 2,
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BMI_WRITE_MEMORY = 3,
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BMI_EXECUTE = 4,
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BMI_SET_APP_START = 5,
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BMI_READ_SOC_REGISTER = 6,
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BMI_READ_SOC_WORD = 6,
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BMI_WRITE_SOC_REGISTER = 7,
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BMI_WRITE_SOC_WORD = 7,
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BMI_GET_TARGET_ID = 8,
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BMI_GET_TARGET_INFO = 8,
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BMI_ROMPATCH_INSTALL = 9,
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BMI_ROMPATCH_UNINSTALL = 10,
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BMI_ROMPATCH_ACTIVATE = 11,
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BMI_ROMPATCH_DEACTIVATE = 12,
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BMI_LZ_STREAM_START = 13, /* should be followed by LZ_DATA */
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BMI_LZ_DATA = 14,
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BMI_NVRAM_PROCESS = 15,
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};
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#define BMI_NVRAM_SEG_NAME_SZ 16
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#define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
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#define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000
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#define BMI_PARAM_FLASH_SECTION_ALL 0x10000
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#define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK 0x7c00
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#define ATH10K_BMI_BOARD_ID_FROM_OTP_LSB 10
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#define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK 0x18000
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#define ATH10K_BMI_CHIP_ID_FROM_OTP_LSB 15
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#define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
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struct bmi_cmd {
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__le32 id; /* enum bmi_cmd_id */
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union {
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struct {
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} done;
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struct {
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__le32 addr;
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__le32 len;
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} read_mem;
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struct {
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__le32 addr;
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__le32 len;
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u8 payload[0];
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} write_mem;
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struct {
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__le32 addr;
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__le32 param;
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} execute;
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struct {
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__le32 addr;
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} set_app_start;
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struct {
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__le32 addr;
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} read_soc_reg;
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struct {
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__le32 addr;
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__le32 value;
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} write_soc_reg;
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struct {
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} get_target_info;
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struct {
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__le32 rom_addr;
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__le32 ram_addr; /* or value */
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__le32 size;
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__le32 activate; /* 0=install, but dont activate */
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} rompatch_install;
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struct {
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__le32 patch_id;
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} rompatch_uninstall;
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struct {
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__le32 count;
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__le32 patch_ids[0]; /* length of @count */
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} rompatch_activate;
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struct {
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__le32 count;
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__le32 patch_ids[0]; /* length of @count */
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} rompatch_deactivate;
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struct {
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__le32 addr;
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} lz_start;
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struct {
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__le32 len; /* max BMI_MAX_DATA_SIZE */
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u8 payload[0]; /* length of @len */
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} lz_data;
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struct {
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u8 name[BMI_NVRAM_SEG_NAME_SZ];
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} nvram_process;
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u8 payload[BMI_MAX_CMDBUF_SIZE];
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};
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} __packed;
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union bmi_resp {
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struct {
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u8 payload[0];
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} read_mem;
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struct {
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__le32 result;
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} execute;
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struct {
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__le32 value;
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} read_soc_reg;
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struct {
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__le32 len;
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__le32 version;
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__le32 type;
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} get_target_info;
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struct {
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__le32 patch_id;
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} rompatch_install;
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struct {
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__le32 patch_id;
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} rompatch_uninstall;
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struct {
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/* 0 = nothing executed
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* otherwise = NVRAM segment return value
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*/
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__le32 result;
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} nvram_process;
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u8 payload[BMI_MAX_CMDBUF_SIZE];
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} __packed;
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struct bmi_target_info {
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u32 version;
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u32 type;
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};
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/* in jiffies */
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#define BMI_COMMUNICATION_TIMEOUT_HZ (3 * HZ)
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#define BMI_CE_NUM_TO_TARG 0
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#define BMI_CE_NUM_TO_HOST 1
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void ath10k_bmi_start(struct ath10k *ar);
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int ath10k_bmi_done(struct ath10k *ar);
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int ath10k_bmi_get_target_info(struct ath10k *ar,
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struct bmi_target_info *target_info);
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int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
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struct bmi_target_info *target_info);
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int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
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void *buffer, u32 length);
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int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
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const void *buffer, u32 length);
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#define ath10k_bmi_read32(ar, item, val) \
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({ \
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int ret; \
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u32 addr; \
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__le32 tmp; \
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\
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addr = host_interest_item_address(HI_ITEM(item)); \
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ret = ath10k_bmi_read_memory(ar, addr, (u8 *)&tmp, 4); \
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if (!ret) \
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*val = __le32_to_cpu(tmp); \
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ret; \
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})
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#define ath10k_bmi_write32(ar, item, val) \
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({ \
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int ret; \
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u32 address; \
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__le32 v = __cpu_to_le32(val); \
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\
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address = host_interest_item_address(HI_ITEM(item)); \
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ret = ath10k_bmi_write_memory(ar, address, \
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(u8 *)&v, sizeof(v)); \
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ret; \
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})
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int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result);
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int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address);
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int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length);
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int ath10k_bmi_fast_download(struct ath10k *ar, u32 address,
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const void *buffer, u32 length);
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int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val);
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int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val);
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#endif /* _BMI_H_ */
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