315 lines
7.5 KiB
C
315 lines
7.5 KiB
C
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/*
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* Marvell Wireless LAN device driver: generic data structures and APIs
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*
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* Copyright (C) 2011-2014, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_DECL_H_
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#define _MWIFIEX_DECL_H_
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#undef pr_fmt
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/wait.h>
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#include <linux/timer.h>
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#include <linux/ieee80211.h>
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#include <uapi/linux/if_arp.h>
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#include <net/cfg80211.h>
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#define MWIFIEX_BSS_COEX_COUNT 2
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#define MWIFIEX_MAX_BSS_NUM (3)
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#define MWIFIEX_DMA_ALIGN_SZ 64
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#define MWIFIEX_RX_HEADROOM 64
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#define MAX_TXPD_SZ 32
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#define INTF_HDR_ALIGN 4
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#define MWIFIEX_MIN_DATA_HEADER_LEN (MWIFIEX_DMA_ALIGN_SZ + INTF_HDR_ALIGN + \
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MAX_TXPD_SZ)
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#define MWIFIEX_MGMT_FRAME_HEADER_SIZE 8 /* sizeof(pkt_type)
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* + sizeof(tx_control)
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*/
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#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2
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#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16
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#define MWIFIEX_MAX_TDLS_PEER_SUPPORTED 8
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#define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE 64
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#define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE 64
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#define MWIFIEX_STA_COEX_AMPDU_DEF_RXWINSIZE 16
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#define MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE 32
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#define MWIFIEX_UAP_COEX_AMPDU_DEF_RXWINSIZE 16
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#define MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE 16
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#define MWIFIEX_11AC_STA_AMPDU_DEF_TXWINSIZE 64
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#define MWIFIEX_11AC_STA_AMPDU_DEF_RXWINSIZE 64
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#define MWIFIEX_11AC_UAP_AMPDU_DEF_TXWINSIZE 64
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#define MWIFIEX_11AC_UAP_AMPDU_DEF_RXWINSIZE 64
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#define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff
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#define MWIFIEX_RATE_BITMAP_MCS0 32
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#define MWIFIEX_RX_DATA_BUF_SIZE (4 * 1024)
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#define MWIFIEX_RX_CMD_BUF_SIZE (2 * 1024)
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#define MAX_BEACON_PERIOD (4000)
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#define MIN_BEACON_PERIOD (50)
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#define MAX_DTIM_PERIOD (100)
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#define MIN_DTIM_PERIOD (1)
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#define MWIFIEX_RTS_MIN_VALUE (0)
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#define MWIFIEX_RTS_MAX_VALUE (2347)
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#define MWIFIEX_FRAG_MIN_VALUE (256)
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#define MWIFIEX_FRAG_MAX_VALUE (2346)
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#define MWIFIEX_WMM_VERSION 0x01
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#define MWIFIEX_WMM_SUBTYPE 0x01
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#define MWIFIEX_RETRY_LIMIT 14
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#define MWIFIEX_SDIO_BLOCK_SIZE 256
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#define MWIFIEX_BUF_FLAG_REQUEUED_PKT BIT(0)
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#define MWIFIEX_BUF_FLAG_BRIDGED_PKT BIT(1)
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#define MWIFIEX_BUF_FLAG_TDLS_PKT BIT(2)
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#define MWIFIEX_BUF_FLAG_EAPOL_TX_STATUS BIT(3)
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#define MWIFIEX_BUF_FLAG_ACTION_TX_STATUS BIT(4)
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#define MWIFIEX_BUF_FLAG_AGGR_PKT BIT(5)
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#define MWIFIEX_BRIDGED_PKTS_THR_HIGH 1024
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#define MWIFIEX_BRIDGED_PKTS_THR_LOW 128
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#define MWIFIEX_TDLS_DISABLE_LINK 0x00
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#define MWIFIEX_TDLS_ENABLE_LINK 0x01
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#define MWIFIEX_TDLS_CREATE_LINK 0x02
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#define MWIFIEX_TDLS_CONFIG_LINK 0x03
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#define MWIFIEX_TDLS_RSSI_HIGH 50
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#define MWIFIEX_TDLS_RSSI_LOW 55
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#define MWIFIEX_TDLS_MAX_FAIL_COUNT 4
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#define MWIFIEX_AUTO_TDLS_IDLE_TIME 10
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/* 54M rates, index from 0 to 11 */
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#define MWIFIEX_RATE_INDEX_MCS0 12
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/* 12-27=MCS0-15(BW20) */
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#define MWIFIEX_BW20_MCS_NUM 15
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/* Rate index for OFDM 0 */
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#define MWIFIEX_RATE_INDEX_OFDM0 4
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#define MWIFIEX_MAX_STA_NUM 3
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#define MWIFIEX_MAX_UAP_NUM 3
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#define MWIFIEX_MAX_P2P_NUM 3
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#define MWIFIEX_A_BAND_START_FREQ 5000
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/* SDIO Aggr data packet special info */
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#define SDIO_MAX_AGGR_BUF_SIZE (256 * 255)
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#define BLOCK_NUMBER_OFFSET 15
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#define SDIO_HEADER_OFFSET 28
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#define MWIFIEX_SIZE_4K 0x4000
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enum mwifiex_bss_type {
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MWIFIEX_BSS_TYPE_STA = 0,
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MWIFIEX_BSS_TYPE_UAP = 1,
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MWIFIEX_BSS_TYPE_P2P = 2,
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MWIFIEX_BSS_TYPE_ANY = 0xff,
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};
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enum mwifiex_bss_role {
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MWIFIEX_BSS_ROLE_STA = 0,
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MWIFIEX_BSS_ROLE_UAP = 1,
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MWIFIEX_BSS_ROLE_ANY = 0xff,
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};
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enum mwifiex_tdls_status {
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TDLS_NOT_SETUP = 0,
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TDLS_SETUP_INPROGRESS,
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TDLS_SETUP_COMPLETE,
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TDLS_SETUP_FAILURE,
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TDLS_LINK_TEARDOWN,
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TDLS_CHAN_SWITCHING,
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TDLS_IN_BASE_CHAN,
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TDLS_IN_OFF_CHAN,
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};
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enum mwifiex_tdls_error_code {
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TDLS_ERR_NO_ERROR = 0,
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TDLS_ERR_INTERNAL_ERROR,
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TDLS_ERR_MAX_LINKS_EST,
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TDLS_ERR_LINK_EXISTS,
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TDLS_ERR_LINK_NONEXISTENT,
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TDLS_ERR_PEER_STA_UNREACHABLE = 25,
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};
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#define BSS_ROLE_BIT_MASK BIT(0)
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#define GET_BSS_ROLE(priv) ((priv)->bss_role & BSS_ROLE_BIT_MASK)
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enum mwifiex_data_frame_type {
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MWIFIEX_DATA_FRAME_TYPE_ETH_II = 0,
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MWIFIEX_DATA_FRAME_TYPE_802_11,
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};
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struct mwifiex_fw_image {
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u8 *helper_buf;
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u32 helper_len;
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u8 *fw_buf;
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u32 fw_len;
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};
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struct mwifiex_802_11_ssid {
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u32 ssid_len;
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u8 ssid[IEEE80211_MAX_SSID_LEN];
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};
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struct mwifiex_wait_queue {
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wait_queue_head_t wait;
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int status;
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};
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struct mwifiex_rxinfo {
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struct sk_buff *parent;
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u8 bss_num;
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u8 bss_type;
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u8 use_count;
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u8 buf_type;
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};
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struct mwifiex_txinfo {
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u32 status_code;
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u8 flags;
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u8 bss_num;
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u8 bss_type;
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u8 aggr_num;
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u32 pkt_len;
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u8 ack_frame_id;
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u64 cookie;
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};
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enum mwifiex_wmm_ac_e {
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WMM_AC_BK,
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WMM_AC_BE,
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WMM_AC_VI,
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WMM_AC_VO
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} __packed;
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struct ieee_types_wmm_ac_parameters {
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u8 aci_aifsn_bitmap;
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u8 ecw_bitmap;
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__le16 tx_op_limit;
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} __packed;
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struct mwifiex_types_wmm_info {
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u8 oui[4];
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u8 subtype;
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u8 version;
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u8 qos_info;
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u8 reserved;
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struct ieee_types_wmm_ac_parameters ac_params[IEEE80211_NUM_ACS];
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} __packed;
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struct mwifiex_arp_eth_header {
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struct arphdr hdr;
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u8 ar_sha[ETH_ALEN];
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u8 ar_sip[4];
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u8 ar_tha[ETH_ALEN];
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u8 ar_tip[4];
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} __packed;
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struct mwifiex_chan_stats {
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u8 chan_num;
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u8 bandcfg;
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u8 flags;
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s8 noise;
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u16 total_bss;
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u16 cca_scan_dur;
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u16 cca_busy_dur;
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} __packed;
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#define MWIFIEX_HIST_MAX_SAMPLES 1048576
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#define MWIFIEX_MAX_RX_RATES 44
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#define MWIFIEX_MAX_AC_RX_RATES 74
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#define MWIFIEX_MAX_SNR 256
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#define MWIFIEX_MAX_NOISE_FLR 256
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#define MWIFIEX_MAX_SIG_STRENGTH 256
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struct mwifiex_histogram_data {
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atomic_t rx_rate[MWIFIEX_MAX_AC_RX_RATES];
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atomic_t snr[MWIFIEX_MAX_SNR];
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atomic_t noise_flr[MWIFIEX_MAX_NOISE_FLR];
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atomic_t sig_str[MWIFIEX_MAX_SIG_STRENGTH];
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atomic_t num_samples;
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};
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struct mwifiex_iface_comb {
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u8 sta_intf;
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u8 uap_intf;
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u8 p2p_intf;
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};
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struct mwifiex_radar_params {
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struct cfg80211_chan_def *chandef;
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u32 cac_time_ms;
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} __packed;
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struct mwifiex_11h_intf_state {
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bool is_11h_enabled;
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bool is_11h_active;
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} __packed;
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#define MWIFIEX_FW_DUMP_IDX 0xff
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#define MWIFIEX_FW_DUMP_MAX_MEMSIZE 0x160000
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#define MWIFIEX_DRV_INFO_IDX 20
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#define FW_DUMP_MAX_NAME_LEN 8
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#define FW_DUMP_HOST_READY 0xEE
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#define FW_DUMP_DONE 0xFF
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#define FW_DUMP_READ_DONE 0xFE
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struct memory_type_mapping {
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u8 mem_name[FW_DUMP_MAX_NAME_LEN];
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u8 *mem_ptr;
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u32 mem_size;
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u8 done_flag;
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};
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enum rdwr_status {
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RDWR_STATUS_SUCCESS = 0,
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RDWR_STATUS_FAILURE = 1,
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RDWR_STATUS_DONE = 2
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};
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enum mwifiex_chan_width {
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CHAN_BW_20MHZ = 0,
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CHAN_BW_10MHZ,
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CHAN_BW_40MHZ,
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CHAN_BW_80MHZ,
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CHAN_BW_8080MHZ,
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CHAN_BW_160MHZ,
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CHAN_BW_5MHZ,
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};
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enum mwifiex_chan_offset {
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SEC_CHAN_NONE = 0,
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SEC_CHAN_ABOVE = 1,
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SEC_CHAN_5MHZ = 2,
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SEC_CHAN_BELOW = 3
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};
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#endif /* !_MWIFIEX_DECL_H_ */
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