145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __RT9465_CHARGER_H
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#define __RT9465_CHARGER_H
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#define RT9465_SLAVE_ADDR 0x4B
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#define RT9465_VERSION_E1 0x00
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#define RT9465_VERSION_E2 0x01
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#define RT9465_VERSION_E3 0x02
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#define RT9465_VERSION_E4 0x03
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#define RT9465_VERSION_E5 0x04
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enum rt9465_reg_addr {
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RT9465_REG_CHG_CTRL0,
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RT9465_REG_CHG_CTRL1,
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RT9465_REG_CHG_CTRL2,
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RT9465_REG_CHG_CTRL3,
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RT9465_REG_CHG_CTRL4,
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RT9465_REG_CHG_CTRL5,
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RT9465_REG_CHG_CTRL6,
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RT9465_REG_CHG_CTRL7,
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RT9465_REG_CHG_CTRL8,
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RT9465_REG_CHG_CTRL9,
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RT9465_REG_CHG_CTRL10,
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RT9465_REG_CHG_CTRL12 = 0x0C,
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RT9465_REG_CHG_CTRL13,
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RT9465_REG_HIDDEN_CTRL2 = 0x12,
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RT9465_REG_HIDDEN_CTRL6 = 0x16,
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RT9465_REG_SYSTEM1 = 0x20,
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RT9465_REG_CHG_STATC = 0x30,
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RT9465_REG_CHG_FAULT,
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RT9465_REG_CHG_IRQ1,
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RT9465_REG_CHG_IRQ2,
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RT9465_REG_CHG_STATC_MASK = 0x40,
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RT9465_REG_CHG_FAULT_MASK,
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RT9465_REG_CHG_IRQ1_MASK,
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RT9465_REG_CHG_IRQ2_MASK,
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RT9465_REG_MAX,
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};
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/* =========================== */
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/* RT9465 Parameter */
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/* =========================== */
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/* uA */
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#define RT9465_ICHG_NUM 20
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#define RT9465_ICHG_MIN 600000
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#define RT9465_ICHG_MAX 2500000
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#define RT9465_ICHG_STEP 100000
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/* uA */
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#define RT9465_IEOC_NUM 11
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#define RT9465_IEOC_MIN 600000
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#define RT9465_IEOC_MAX 1600000
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#define RT9465_IEOC_STEP 100000
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/* uV */
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#define RT9465_MIVR_NUM 128
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#define RT9465_MIVR_MIN 3900000
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#define RT9465_MIVR_MAX 13400000
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#define RT9465_MIVR_STEP 100000
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/* uV */
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#define RT9465_BAT_VOREG_NUM 64
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#define RT9465_BAT_VOREG_MIN 3800000
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#define RT9465_BAT_VOREG_MAX 5060000
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#define RT9465_BAT_VOREG_STEP 20000
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/* ADC Temperature */
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/* degree */
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#define RT9465_ADC_RPT_NUM 15
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#define RT9465_ADC_RPT_MIN 60
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#define RT9465_ADC_RPT_MAX 116
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#define RT9465_ADC_RPT_STEP 4
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/* ========== CHG_CTRL0 0x00 ============ */
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#define RT9465_SHIFT_RST 7
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#define RT9465_MASK_RST (1 << RT9465_SHIFT_RST)
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/* ========== CHG_CTRL1 0x01 ============ */
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#define RT9465_SHIFT_CHG_EN 7
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#define RT9465_MASK_CHG_EN (1 << RT9465_SHIFT_CHG_EN)
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/* ========== CHG_CTRL3 0x03 ============ */
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#define RT9465_SHIFT_BAT_VOREG 2
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#define RT9465_MASK_BAT_VOREG 0xFC
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/* ========== CHG_CTRL5 0x05 ============ */
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#define RT9465_SHIFT_MIVR 1
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#define RT9465_SHIFT_MIVR_EN 0
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#define RT9465_MASK_MIVR 0xFE
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#define RT9465_MASK_MIVR_EN (1 << RT9465_SHIFT_MIVR_EN)
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/* ========== CHG_CTRL6 0x06 ============ */
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#define RT9465_SHIFT_ICHG 3
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#define RT9465_MASK_ICHG 0xF8
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/* ========== CHG_CTRL7 0x07 ============ */
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#define RT9465_SHIFT_IEOC 4
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#define RT9465_MASK_IEOC 0xF0
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/* ========== CHG_CTRL8 0x08 ============ */
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#define RT9465_SHIFT_TE_EN 7
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#define RT9465_MASK_TE_EN (1 << RT9465_SHIFT_TE_EN)
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/* ========== CHG_CTRL9 0x09 ============ */
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#define RT9465_SHIFT_TMR_EN 3
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#define RT9465_SHIFT_WT_FC 5
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#define RT9465_MASK_TMR_EN (1 << RT9465_SHIFT_TMR_EN)
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#define RT9465_MASK_WT_FC 0xE0
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/* ========== CHG_CTRL10 0x0A ============ */
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#define RT9465_SHIFT_WDT_EN 7
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#define RT9465_MASK_WDT_EN (1 << RT9465_SHIFT_WDT_EN)
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/* ========== CHG_CTRL12 0x0C ============ */
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#define RT9465_SHIFT_ADC_RPT 4
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#define RT9465_MASK_ADC_RPT 0xF0
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/* ========== SYSTEM1 0x20 ============ */
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#define RT9465_SHIFT_CHG_STAT 6
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#define RT9465_SHIFT_VERSION 1
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#define RT9465_MASK_CHG_STAT 0xC0
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#define RT9465_MASK_VERSION 0x0E
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/* ========== STATC 0x30 ============ */
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#define RT9465_SHIFT_CHG_MIVR 6
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#define RT9465_MASK_CHG_MIVR (1 << RT9465_SHIFT_CHG_MIVR)
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#endif /* __RT9465_CHARGER_H */
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