135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __RT9750_LOAD_SWITCH_H
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#define __RT9750_LOAD_SWITCH_H
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#define RT9750_SLAVE_ADDR 0x67
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#define RT9750_DEVICE_ID 0x00
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#define RT9750_CHIP_REV_E1 0x00
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enum rt9466_reg_addr {
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RT9750_REG_CORE_CTRL0 = 0x00,
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RT9750_REG_EVENT1_MASK,
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RT9750_REG_EVENT2_MASK,
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RT9750_REG_EVENT1,
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RT9750_REG_EVENT2,
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RT9750_REG_EVENT1_EN,
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RT9750_REG_CONTROL,
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RT9750_REG_ADC_CTRL,
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RT9750_REG_SAMPLE_EN,
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RT9750_REG_PROT_DLYOCP,
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RT9750_REG_VBUS_OVP,
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RT9750_REG_VOUT_REG,
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RT9750_REG_VDROP_OVP,
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RT9750_REG_VDROP_ALM,
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RT9750_REG_VBAT_REG,
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RT9750_REG_IBUS_OCP = 0x10,
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RT9750_REG_TBUS_OTP,
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RT9750_REG_TBAT_OTP,
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RT9750_REG_VBUS_ADC2,
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RT9750_REG_VBUS_ADC1,
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RT9750_REG_IBUS_ADC2,
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RT9750_REG_IBUS_ADC1,
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RT9750_REG_VOUT_ADC2,
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RT9750_REG_VOUT_ADC1,
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RT9750_REG_VDROP_ADC2,
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RT9750_REG_VDROP_ADC1,
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RT9750_REG_VBAT_ADC2,
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RT9750_REG_VBAT_ADC1,
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RT9750_REG_TBUS_ADC2 = 0x1F,
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RT9750_REG_TBUS_ADC1,
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RT9750_REG_TBAT_ADC2,
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RT9750_REG_TBAT_ADC1,
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RT9750_REG_TDIE_ADC1,
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RT9750_REG_EVENT_STATUS1,
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RT9750_REG_EVENT_STATUS2,
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RT9750_REG_EVENT_STATUS,
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};
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#define RT9750_VOUT_MAX 5000000
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#define RT9750_VOUT_MIN 4200000
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#define RT9750_VOUT_STEP 10000
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#define RT9750_VOUT_NUM 81
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#define RT9750_VBAT_MAX 5000000
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#define RT9750_VBAT_MIN 4200000
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#define RT9750_VBAT_STEP 10000
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#define RT9750_VBAT_NUM 81
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#define RT9750_IOCOCP_MAX 6500000
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#define RT9750_IOCOCP_MIN 0
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#define RT9750_IOCOCP_STEP 500000
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#define RT9750_IOCOCP_NUM 14
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#define RT9750_IBUSOC_MAX 6350000
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#define RT9750_IBUSOC_MIN 0
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#define RT9750_IBUSOC_STEP 50000
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#define RT9750_IBUSOC_NUM 128
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#define RT9750_VBUSOV_MAX 6500000
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#define RT9750_VBUSOV_MIN 4200000
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#define RT9750_VBUSOV_STEP 25000
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#define RT9750_VBUSOV_NUM 93
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/* ========== RT9750_REG_CONTROL 0x06 ============ */
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#define RT9750_SHIFT_CHG_EN 4
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#define RT9750_SHIFT_WDT 2
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#define RT9750_MASK_CHG_EN (1 << RT9750_SHIFT_CHG_EN)
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#define RT9750_MASK_WDT 0x0C
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/* ========== RT9750_REG_PROT_DLYOCP 0x09 ============ */
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#define RT9750_SHIFT_IOCOCP 4
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#define RT9750_MASK_IOCOCP 0xF0
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/* ========== RT9750_REG_VBUS_OVP 0x09 ============ */
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#define RT9750_SHIFT_VBUSOVP 0
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#define RT9750_MASK_VBUSOVP 0x7F
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/* ========== RT9750_REG_VOUT_REG 0x0B ============ */
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#define RT9750_SHIFT_VOUT 0
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#define RT9750_MASK_VOUT 0x7F
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/* ========== RT9750_REG_VBAT_REG 0x0E ============ */
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#define RT9750_SHIFT_VBAT 0
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#define RT9750_MASK_VBAT 0x7F
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/* ========== RT9750_REG_IBUS_OC 0x10 ============ */
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#define RT9750_SHIFT_IBUS_OCP 0
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#define RT9750_MASK_IBUS_OCP 0x7F
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/* ========== RT9750_REG_VBUS_ADC2 0x13 ============ */
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#define RT9750_SHIFT_VBUS_ADC2 0
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#define RT9750_MASK_VBUS_ADC2 0x1F
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/* ========== RT9750_REG_IBUS_ADC2 0x15 ============ */
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#define RT9750_SHIFT_IBUS_ADC2 0
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#define RT9750_MASK_IBUS_ADC2 0x1F
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/* ========== RT9750_REG_VOUT_ADC2 0x17 ============ */
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#define RT9750_SHIFT_VOUT_ADC2 0
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#define RT9750_MASK_VOUT_ADC2 0x1F
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/* ========== RT9750_REG_VDROP_ADC2 0x19 ============ */
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#define RT9750_SHIFT_VDROP_ADC2 0
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#define RT9750_MASK_VDROP_ADC2 0x03
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/* ========== RT9750_REG_VBAT_ADC2 0x1B ============ */
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#define RT9750_SHIFT_VBAT_ADC2 0
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#define RT9750_MASK_VBAT_ADC2 0x1F
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/* ========== RT9750_REG_TBUS_ADC2 0x1F ============ */
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#define RT9750_SHIFT_TBUS_ADC2 0
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#define RT9750_MASK_TBUS_ADC2 0x0F
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/* ========== RT9750_REG_TBAT_ADC2 0x21 ============ */
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#define RT9750_SHIFT_TBAT_ADC2 0
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#define RT9750_MASK_TBAT_ADC2 0x0F
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#endif /* __RT9750_LOAD_SWITCH_H */
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