202 lines
6.5 KiB
C
202 lines
6.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* FPGA Framework
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*
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* Copyright (C) 2013-2016 Altera Corporation
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* Copyright (C) 2017 Intel Corporation
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*/
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#ifndef _LINUX_FPGA_MGR_H
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#define _LINUX_FPGA_MGR_H
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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struct fpga_manager;
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struct sg_table;
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/**
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* enum fpga_mgr_states - fpga framework states
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* @FPGA_MGR_STATE_UNKNOWN: can't determine state
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* @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
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* @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
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* @FPGA_MGR_STATE_RESET: FPGA in reset state
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* @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
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* @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
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* @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
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* @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
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* @FPGA_MGR_STATE_WRITE: writing image to FPGA
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* @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
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* @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps
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* @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
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* @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
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*/
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enum fpga_mgr_states {
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/* default FPGA states */
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FPGA_MGR_STATE_UNKNOWN,
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FPGA_MGR_STATE_POWER_OFF,
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FPGA_MGR_STATE_POWER_UP,
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FPGA_MGR_STATE_RESET,
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/* getting an image for loading */
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FPGA_MGR_STATE_FIRMWARE_REQ,
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FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
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/* write sequence: init, write, complete */
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FPGA_MGR_STATE_WRITE_INIT,
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FPGA_MGR_STATE_WRITE_INIT_ERR,
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FPGA_MGR_STATE_WRITE,
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FPGA_MGR_STATE_WRITE_ERR,
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FPGA_MGR_STATE_WRITE_COMPLETE,
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FPGA_MGR_STATE_WRITE_COMPLETE_ERR,
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/* fpga is programmed and operating */
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FPGA_MGR_STATE_OPERATING,
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};
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/**
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* DOC: FPGA Manager flags
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*
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* Flags used in the &fpga_image_info->flags field
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*
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* %FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
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*
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* %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
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*
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* %FPGA_MGR_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted
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*
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* %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
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*
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* %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed
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*/
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#define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
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#define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
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#define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
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#define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
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#define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
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/**
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* struct fpga_image_info - information specific to a FPGA image
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* @flags: boolean flags as defined above
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* @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
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* @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
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* @config_complete_timeout_us: maximum time for FPGA to switch to operating
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* status in the write_complete op.
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* @firmware_name: name of FPGA image firmware file
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* @sgt: scatter/gather table containing FPGA image
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* @buf: contiguous buffer containing FPGA image
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* @count: size of buf
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* @region_id: id of target region
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* @dev: device that owns this
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* @overlay: Device Tree overlay
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*/
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struct fpga_image_info {
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u32 flags;
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u32 enable_timeout_us;
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u32 disable_timeout_us;
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u32 config_complete_timeout_us;
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char *firmware_name;
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struct sg_table *sgt;
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const char *buf;
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size_t count;
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int region_id;
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struct device *dev;
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#ifdef CONFIG_OF
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struct device_node *overlay;
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#endif
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};
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/**
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* struct fpga_manager_ops - ops for low level fpga manager drivers
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* @initial_header_size: Maximum number of bytes that should be passed into write_init
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* @state: returns an enum value of the FPGA's state
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* @status: returns status of the FPGA, including reconfiguration error code
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* @write_init: prepare the FPGA to receive confuration data
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* @write: write count bytes of configuration data to the FPGA
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* @write_sg: write the scatter list of configuration data to the FPGA
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* @write_complete: set FPGA to operating state after writing is done
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* @fpga_remove: optional: Set FPGA into a specific state during driver remove
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* @groups: optional attribute groups.
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*
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* fpga_manager_ops are the low level functions implemented by a specific
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* fpga manager driver. The optional ones are tested for NULL before being
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* called, so leaving them out is fine.
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*/
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struct fpga_manager_ops {
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size_t initial_header_size;
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enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
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u64 (*status)(struct fpga_manager *mgr);
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int (*write_init)(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count);
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int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
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int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
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int (*write_complete)(struct fpga_manager *mgr,
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struct fpga_image_info *info);
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void (*fpga_remove)(struct fpga_manager *mgr);
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const struct attribute_group **groups;
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};
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/* FPGA manager status: Partial/Full Reconfiguration errors */
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#define FPGA_MGR_STATUS_OPERATION_ERR BIT(0)
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#define FPGA_MGR_STATUS_CRC_ERR BIT(1)
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#define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2)
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#define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3)
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#define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4)
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/**
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* struct fpga_compat_id - id for compatibility check
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*
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* @id_h: high 64bit of the compat_id
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* @id_l: low 64bit of the compat_id
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*/
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struct fpga_compat_id {
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u64 id_h;
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u64 id_l;
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};
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/**
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* struct fpga_manager - fpga manager structure
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* @name: name of low level fpga manager
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* @dev: fpga manager device
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* @ref_mutex: only allows one reference to fpga manager
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* @state: state of fpga manager
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* @compat_id: FPGA manager id for compatibility check.
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* @mops: pointer to struct of fpga manager ops
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* @priv: low level driver private date
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*/
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struct fpga_manager {
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const char *name;
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struct device dev;
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struct mutex ref_mutex;
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enum fpga_mgr_states state;
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struct fpga_compat_id *compat_id;
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const struct fpga_manager_ops *mops;
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void *priv;
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};
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#define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
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struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
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void fpga_image_info_free(struct fpga_image_info *info);
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int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info);
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int fpga_mgr_lock(struct fpga_manager *mgr);
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void fpga_mgr_unlock(struct fpga_manager *mgr);
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struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
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struct fpga_manager *fpga_mgr_get(struct device *dev);
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void fpga_mgr_put(struct fpga_manager *mgr);
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struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
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const struct fpga_manager_ops *mops,
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void *priv);
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void fpga_mgr_free(struct fpga_manager *mgr);
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int fpga_mgr_register(struct fpga_manager *mgr);
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void fpga_mgr_unregister(struct fpga_manager *mgr);
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#endif /*_LINUX_FPGA_MGR_H */
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