120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_GIC_EXTEND_H
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#define __MTK_GIC_EXTEND_H
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#define MT_EDGE_SENSITIVE 0
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#define MT_LEVEL_SENSITIVE 1
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#define MT_POLARITY_LOW 0
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#define MT_POLARITY_HIGH 1
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#define INTID_INVALID 1024
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#ifndef FIQ_SMP_CALL_SGI
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#define FIQ_SMP_CALL_SGI 13
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#endif
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#define GIC_IIDR 0x8
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#define GICD_V3_IIDR_GIC600 0x2
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#define GICD_V3_IIDR_PROD_ID_SHIFT 24
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#include <linux/irq.h>
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typedef void (*fiq_isr_handler) (void *arg, void *regs, void *svc_sp);
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enum {
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IRQ_MASK_HEADER = 0xF1F1F1F1,
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IRQ_MASK_FOOTER = 0xF2F2F2F2
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};
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struct mtk_irq_mask {
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unsigned int header; /* for error checking */
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__u32 mask0;
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__u32 mask1;
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__u32 mask2;
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__u32 mask3;
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__u32 mask4;
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__u32 mask5;
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__u32 mask6;
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__u32 mask7;
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__u32 mask8;
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__u32 mask9;
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__u32 mask10;
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__u32 mask11;
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__u32 mask12;
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unsigned int footer; /* for error checking */
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};
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unsigned int get_hardware_irq(unsigned int virq);
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void mt_irq_unmask_for_sleep(unsigned int hwirq);
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void mt_irq_unmask_for_sleep_ex(unsigned int virq);
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void mt_irq_mask_for_sleep(unsigned int virq);
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int mt_irq_mask_all(struct mtk_irq_mask *mask);
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int mt_irq_mask_restore(struct mtk_irq_mask *mask);
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void mt_irq_set_pending_for_sleep(unsigned int irq);
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extern u32 mt_irq_get_pending_vec(u32 start_irq);
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extern void mt_irq_set_pending(unsigned int irq);
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extern void mt_irq_set_pending_hw(unsigned int hwirq);
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extern unsigned int mt_irq_get_pending(unsigned int irq);
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extern unsigned int mt_irq_get_pending_hw(unsigned int hwirq);
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extern u32 mt_irq_get_pol(u32 irq);
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extern u32 mt_irq_get_pol_hw(u32 hwirq);
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extern void mt_irq_dump_status(int irq);
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void mt_gic_set_priority(unsigned int irq);
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void mt_set_irq_priority(unsigned int irq, unsigned int priority);
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unsigned int mt_get_irq_priority(unsigned int irq);
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#ifdef CONFIG_FAST_CIRQ_CLONE_FLUSH
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extern void __iomem *get_dist_base(void);
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extern u32 mt_irq_get_en_hw(unsigned int hwirq);
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#endif
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#if defined(CONFIG_FIQ_GLUE)
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int request_fiq(int irq, fiq_isr_handler handler,
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unsigned long irq_flags, void *arg);
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void irq_raise_softirq(const struct cpumask *mask, unsigned int irq);
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#endif
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/* set the priority mask to 0x10 for masking all irqs to this cpu */
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void gic_set_primask(void);
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/* restore the priority mask value */
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void gic_clear_primask(void);
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int add_cpu_to_prefer_schedule_domain(unsigned int cpu);
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int remove_cpu_from_prefer_schedule_domain(unsigned int cpu);
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#ifdef CONFIG_MTK_SYSIRQ
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static inline struct irq_data *get_gic_irq_data(struct irq_data *d)
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{
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return d->parent_data;
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}
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#endif
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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#ifdef CONFIG_MTK_SYSIRQ
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d = get_gic_irq_data(d);
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#endif
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return d->hwirq;
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}
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static inline unsigned int virq_to_hwirq(unsigned int virq)
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{
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struct irq_desc *desc;
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unsigned int hwirq;
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desc = irq_to_desc(virq);
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if (desc) {
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hwirq = gic_irq(&desc->irq_data);
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} else {
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WARN_ON(!desc);
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hwirq = INTID_INVALID;
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}
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return hwirq;
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}
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#endif
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