81 lines
1.6 KiB
C
81 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef MTK_IOMMU_SMI_H
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#define MTK_IOMMU_SMI_H
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#include <linux/bitops.h>
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#include <linux/device.h>
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#ifdef CONFIG_MTK_SMI
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#define MTK_LARB_NR_MAX 32
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#define MTK_SMI_MMU_EN(port) BIT(port)
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#define RESET_CELL_NUM (2)
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#define MAX_LARB_FOR_CLAMP (6)
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#define MAX_COMMON_FOR_CLAMP (3)
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struct mtk_smi_larb_iommu {
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struct device *dev;
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unsigned int mmu;
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};
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struct mtk_smi_iommu {
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unsigned int larb_nr;
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struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
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};
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#endif
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#if IS_ENABLED(CONFIG_MTK_SMI_EXT)
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#include <linux/platform_device.h>
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struct mtk_smi_pair {
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u32 off;
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u32 val;
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};
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struct mtk_smi_dev {
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u32 id;
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struct device *dev;
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void __iomem *base;
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u32 *mmu;
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u32 nr_clks;
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struct clk **clks;
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atomic_t clk_cnts;
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u32 nr_conf_pairs;
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struct mtk_smi_pair *conf_pairs;
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u32 nr_scen_pairs;
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struct mtk_smi_pair **scen_pairs;
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u32 power_reset_pa[MAX_LARB_FOR_CLAMP];
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void __iomem *power_reset_reg[MAX_LARB_FOR_CLAMP];
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u32 power_reset_value[MAX_LARB_FOR_CLAMP];
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u32 comm_reset_pa[MAX_LARB_FOR_CLAMP];
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void __iomem *comm_reset_reg[MAX_LARB_FOR_CLAMP];
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u32 comm_reset_value[MAX_LARB_FOR_CLAMP];
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bool comm_reset;
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bool comm_clamp_enable;
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u32 comm_clamp_value[MAX_LARB_FOR_CLAMP];
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};
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s32 mtk_smi_clk_enable(struct mtk_smi_dev *smi);
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void mtk_smi_clk_disable(struct mtk_smi_dev *smi);
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struct mtk_smi_dev *mtk_smi_dev_get(const u32 id);
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s32 mtk_smi_conf_set(const struct mtk_smi_dev *smi, const u32 scen_id);
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s32 smi_register(void);
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s32 smi_get_dev_num(void);
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s32 smi_larb_port_check(void);
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#endif
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#endif
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