181 lines
6.9 KiB
C
181 lines
6.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt6768-afe-clk.h -- Mediatek 6768 afe clock ctrl definition
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*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Michael Hsiao <michael.hsiao@mediatek.com>
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*/
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#ifndef _MT6768_AFE_CLOCK_CTRL_H_
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#define _MT6768_AFE_CLOCK_CTRL_H_
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#define AP_PLL_CON3 0x000c
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#define APLL1_TUNER_CON0 0x0040
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#define APLL1_CON1 0x030c
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#define APLL1_CON2 0x0310
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#define APMIXEDSYS_MAX_LENGTH APLL1_CON2
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#define CLK_CFG_3 0x0070
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#define CLK_CFG_4 0x0080
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#define CLK_AUDDIV_0 0x0320
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#define CLK_AUDDIV_1 0x0324
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#define CLK_AUDDIV_2 0x0328
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#define CKSYS_AUD_TOP_CFG 0x032c
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#define CKSYS_AUD_TOP_MON 0x0330
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#define CLK_MAX_LENGTH CKSYS_AUD_TOP_MON
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/* CLK_CFG_4 */
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#define CLK_AUD_INTBUS_SEL_SFT 0
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#define CLK_AUD_INTBUS_SEL_MASK 0x3
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#define CLK_AUD_INTBUS_SEL_MASK_SFT (0x3 << 0)
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/* CLK_AUDDIV_0 */
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#define APLL_PDN_RESERVE0_SFT 0
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#define APLL_PDN_RESERVE0_MASK 0x1
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#define APLL_PDN_RESERVE0_MASK_SFT (0x1 << 0)
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#define APLL_PDN_RESERVE1_SFT 1
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#define APLL_PDN_RESERVE1_MASK 0x1
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#define APLL_PDN_RESERVE1_MASK_SFT (0x1 << 1)
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#define APLL12_DIV0_PDN_SFT 2
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#define APLL12_DIV0_PDN_MASK 0x1
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#define APLL12_DIV0_PDN_MASK_SFT (0x1 << 2)
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#define APLL12_DIV1_PDN_SFT 3
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#define APLL12_DIV1_PDN_MASK 0x1
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#define APLL12_DIV1_PDN_MASK_SFT (0x1 << 3)
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#define APLL12_DIV2_PDN_SFT 4
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#define APLL12_DIV2_PDN_MASK 0x1
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#define APLL12_DIV2_PDN_MASK_SFT (0x1 << 4)
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#define APLL12_DIV3_PDN_SFT 5
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#define APLL12_DIV3_PDN_MASK 0x1
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#define APLL12_DIV3_PDN_MASK_SFT (0x1 << 5)
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#define APLL12_DIV4_PDN_SFT 6
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#define APLL12_DIV4_PDN_MASK 0x1
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#define APLL12_DIV4_PDN_MASK_SFT (0x1 << 6)
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#define APLL12_DIVB_PDN_SFT 7
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#define APLL12_DIVB_PDN_MASK 0x1
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#define APLL12_DIVB_PDN_MASK_SFT (0x1 << 7)
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#define APLL_I2S0_MCK_SEL_SFT 8
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#define APLL_I2S0_MCK_SEL_MASK 0x1
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#define APLL_I2S0_MCK_SEL_MASK_SFT (0x1 << 8)
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#define APLL_I2S1_MCK_SEL_SFT 9
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#define APLL_I2S1_MCK_SEL_MASK 0x1
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#define APLL_I2S1_MCK_SEL_MASK_SFT (0x1 << 9)
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#define APLL_I2S2_MCK_SEL_SFT 10
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#define APLL_I2S2_MCK_SEL_MASK 0x1
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#define APLL_I2S2_MCK_SEL_MASK_SFT (0x1 << 10)
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#define APLL_I2S3_MCK_SEL_SFT 11
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#define APLL_I2S3_MCK_SEL_MASK 0x1
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#define APLL_I2S3_MCK_SEL_MASK_SFT (0x1 << 11)
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#define APLL_I2S4_MCK_SEL_SFT 12
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#define APLL_I2S4_MCK_SEL_MASK 0x1
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#define APLL_I2S4_MCK_SEL_MASK_SFT (0x1 << 12)
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#define APLL1_DIV0_INV_SFT 16
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#define APLL1_DIV0_INV_MASK 0x1
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#define APLL1_DIV0_INV_MASK_SFT (0x1 << 16)
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#define APLL2_DIV0_INV_SFT 17
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#define APLL2_DIV0_INV_MASK 0x1
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#define APLL2_DIV0_INV_MASK_SFT (0x1 << 17)
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#define APLL12_DIV0_INV_SFT 18
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#define APLL12_DIV0_INV_MASK 0x1
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#define APLL12_DIV0_INV_MASK_SFT (0x1 << 18)
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#define APLL12_DIV1_INV_SFT 19
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#define APLL12_DIV1_INV_MASK 0x1
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#define APLL12_DIV1_INV_MASK_SFT (0x1 << 19)
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#define APLL12_DIV2_INV_SFT 20
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#define APLL12_DIV2_INV_MASK 0x1
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#define APLL12_DIV2_INV_MASK_SFT (0x1 << 20)
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#define APLL12_DIV3_INV_SFT 21
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#define APLL12_DIV3_INV_MASK 0x1
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#define APLL12_DIV3_INV_MASK_SFT (0x1 << 21)
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#define APLL12_DIV4_INV_SFT 22
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#define APLL12_DIV4_INV_MASK 0x1
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#define APLL12_DIV4_INV_MASK_SFT (0x1 << 22)
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#define APLL12_DIVB_INV_SFT 23
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#define APLL12_DIVB_INV_MASK 0x1
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#define APLL12_DIVB_INV_MASK_SFT (0x1 << 23)
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#define APLL1_CK_DIV0_SFT 24
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#define APLL1_CK_DIV0_MASK 0xf
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#define APLL1_CK_DIV0_MASK_SFT (0xf << 24)
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#define APLL2_CK_DIV0_SFT 28
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#define APLL2_CK_DIV0_MASK 0xf
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#define APLL2_CK_DIV0_MASK_SFT (0xf << 28)
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/* CLK_AUDDIV_1 */
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#define APLL12_CK_DIV0_SFT 0
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#define APLL12_CK_DIV0_MASK 0xff
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#define APLL12_CK_DIV0_MASK_SFT (0xff << 0)
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#define APLL12_CK_DIV1_SFT 8
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#define APLL12_CK_DIV1_MASK 0xff
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#define APLL12_CK_DIV1_MASK_SFT (0xff << 8)
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#define APLL12_CK_DIV2_SFT 16
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#define APLL12_CK_DIV2_MASK 0xff
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#define APLL12_CK_DIV2_MASK_SFT (0xff << 16)
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#define APLL12_CK_DIV3_SFT 24
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#define APLL12_CK_DIV3_MASK 0xff
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#define APLL12_CK_DIV3_MASK_SFT (0xff << 24)
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/* CLK_AUDDIV_2 */
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#define APLL12_CK_DIV4_SFT 0
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#define APLL12_CK_DIV4_MASK 0xff
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#define APLL12_CK_DIV4_MASK_SFT (0xff << 0)
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#define APLL12_CK_DIVB_SFT 8
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#define APLL12_CK_DIVB_MASK 0xff
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#define APLL12_CK_DIVB_MASK_SFT (0xff << 8)
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#define APLL12_CK_RESERVE_SFT 16
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#define APLL12_CK_RESERVE_MASK 0x1
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#define APLL12_CK_RESERVE_MASK_SFT (0x1 << 16)
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/* AUD_TOP_CFG */
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#define AUD_TOP_CFG_SFT 0
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#define AUD_TOP_CFG_MASK 0xffffffff
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#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
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/* AUD_TOP_MON */
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#define AUD_TOP_MON_SFT 0
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#define AUD_TOP_MON_MASK 0xffffffff
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#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0)
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/* APLL */
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#define APLL1_W_NAME "APLL1"
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#define APLL2_W_NAME "APLL2"
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enum {
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MT6768_APLL1 = 0,
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MT6768_APLL2,
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};
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struct mtk_base_afe;
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int mt6768_init_clock(struct mtk_base_afe *afe);
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int mt6768_afe_enable_clock(struct mtk_base_afe *afe);
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void mt6768_afe_disable_clock(struct mtk_base_afe *afe);
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int mt6768_afe_suspend_clock(struct mtk_base_afe *afe);
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int mt6768_afe_resume_clock(struct mtk_base_afe *afe);
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int mt6768_afe_dram_request(struct device *dev);
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int mt6768_afe_dram_release(struct device *dev);
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int mt6768_apll1_enable(struct mtk_base_afe *afe);
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void mt6768_apll1_disable(struct mtk_base_afe *afe);
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int mt6768_apll2_enable(struct mtk_base_afe *afe);
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void mt6768_apll2_disable(struct mtk_base_afe *afe);
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int mt6768_get_apll_rate(struct mtk_base_afe *afe, int apll);
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int mt6768_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
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int mt6768_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
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extern void aud_intbus_mux_sel(unsigned int aud_idx);
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/* these will be replaced by using CCF */
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int mt6768_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
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void mt6768_mck_disable(struct mtk_base_afe *afe, int mck_id);
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unsigned int get_cksys_reg(unsigned int offset);
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void set_cksys_reg(unsigned int offset, unsigned int value, unsigned int mask);
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unsigned int get_apmixed_reg(unsigned int offset);
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#endif
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