554 lines
14 KiB
C
554 lines
14 KiB
C
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Author: Damien Lespiau <damien.lespiau@intel.com>
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*
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*/
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#include <linux/seq_file.h>
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include "intel_drv.h"
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static const char * const pipe_crc_sources[] = {
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"none",
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"plane1",
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"plane2",
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"pf",
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"pipe",
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"TV",
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"DP-B",
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"DP-C",
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"DP-D",
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"auto",
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};
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static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
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uint32_t *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source)
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{
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struct drm_device *dev = &dev_priv->drm;
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struct intel_encoder *encoder;
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struct intel_crtc *crtc;
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struct intel_digital_port *dig_port;
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int ret = 0;
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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drm_modeset_lock_all(dev);
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for_each_intel_encoder(dev, encoder) {
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if (!encoder->base.crtc)
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continue;
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crtc = to_intel_crtc(encoder->base.crtc);
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if (crtc->pipe != pipe)
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continue;
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switch (encoder->type) {
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case INTEL_OUTPUT_TVOUT:
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*source = INTEL_PIPE_CRC_SOURCE_TV;
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break;
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case INTEL_OUTPUT_DP:
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case INTEL_OUTPUT_EDP:
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dig_port = enc_to_dig_port(&encoder->base);
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switch (dig_port->base.port) {
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case PORT_B:
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*source = INTEL_PIPE_CRC_SOURCE_DP_B;
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break;
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case PORT_C:
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*source = INTEL_PIPE_CRC_SOURCE_DP_C;
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break;
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case PORT_D:
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*source = INTEL_PIPE_CRC_SOURCE_DP_D;
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break;
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default:
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WARN(1, "nonexisting DP port %c\n",
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port_name(dig_port->base.port));
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break;
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}
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break;
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default:
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break;
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}
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}
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drm_modeset_unlock_all(dev);
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return ret;
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}
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static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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uint32_t *val)
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{
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bool need_stable_symbols = false;
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
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int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
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if (ret)
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return ret;
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}
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_B:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_C:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_D:
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if (!IS_CHERRYVIEW(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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/*
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* When the pipe CRC tap point is after the transcoders we need
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* to tweak symbol-level features to produce a deterministic series of
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* symbols for a given frame. We need to reset those features only once
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* a frame (instead of every nth symbol):
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* - DC-balance: used to ensure a better clock recovery from the data
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* link (SDVO)
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* - DisplayPort scrambling: used for EMI reduction
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*/
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if (need_stable_symbols) {
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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tmp |= DC_BALANCE_RESET_VLV;
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switch (pipe) {
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case PIPE_A:
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tmp |= PIPE_A_SCRAMBLE_RESET;
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break;
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case PIPE_B:
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tmp |= PIPE_B_SCRAMBLE_RESET;
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break;
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case PIPE_C:
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tmp |= PIPE_C_SCRAMBLE_RESET;
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break;
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default:
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return -EINVAL;
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}
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I915_WRITE(PORT_DFT2_G4X, tmp);
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}
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return 0;
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}
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static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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uint32_t *val)
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{
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bool need_stable_symbols = false;
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
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int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
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if (ret)
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return ret;
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}
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
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break;
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case INTEL_PIPE_CRC_SOURCE_TV:
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if (!SUPPORTS_TV(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_B:
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if (!IS_G4X(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_C:
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if (!IS_G4X(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_D:
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if (!IS_G4X(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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/*
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* When the pipe CRC tap point is after the transcoders we need
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* to tweak symbol-level features to produce a deterministic series of
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* symbols for a given frame. We need to reset those features only once
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* a frame (instead of every nth symbol):
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* - DC-balance: used to ensure a better clock recovery from the data
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* link (SDVO)
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* - DisplayPort scrambling: used for EMI reduction
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*/
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if (need_stable_symbols) {
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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WARN_ON(!IS_G4X(dev_priv));
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I915_WRITE(PORT_DFT_I9XX,
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I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
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if (pipe == PIPE_A)
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tmp |= PIPE_A_SCRAMBLE_RESET;
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else
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tmp |= PIPE_B_SCRAMBLE_RESET;
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I915_WRITE(PORT_DFT2_G4X, tmp);
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}
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return 0;
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}
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static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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switch (pipe) {
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case PIPE_A:
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tmp &= ~PIPE_A_SCRAMBLE_RESET;
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break;
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case PIPE_B:
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tmp &= ~PIPE_B_SCRAMBLE_RESET;
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break;
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case PIPE_C:
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tmp &= ~PIPE_C_SCRAMBLE_RESET;
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break;
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default:
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return;
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}
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if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
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tmp &= ~DC_BALANCE_RESET_VLV;
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I915_WRITE(PORT_DFT2_G4X, tmp);
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}
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static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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if (pipe == PIPE_A)
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tmp &= ~PIPE_A_SCRAMBLE_RESET;
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else
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tmp &= ~PIPE_B_SCRAMBLE_RESET;
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I915_WRITE(PORT_DFT2_G4X, tmp);
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if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
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I915_WRITE(PORT_DFT_I9XX,
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I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
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}
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}
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static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
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uint32_t *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PLANE1:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE2:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
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bool enable)
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{
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struct drm_device *dev = &dev_priv->drm;
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
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struct intel_crtc_state *pipe_config;
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struct drm_atomic_state *state;
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struct drm_modeset_acquire_ctx ctx;
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int ret = 0;
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drm_modeset_acquire_init(&ctx, 0);
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state = drm_atomic_state_alloc(dev);
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if (!state) {
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ret = -ENOMEM;
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goto unlock;
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}
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state->acquire_ctx = &ctx;
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retry:
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pipe_config = intel_atomic_get_crtc_state(state, crtc);
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if (IS_ERR(pipe_config)) {
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ret = PTR_ERR(pipe_config);
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goto put_state;
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}
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if (HAS_IPS(dev_priv)) {
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/*
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* When IPS gets enabled, the pipe CRC changes. Since IPS gets
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* enabled and disabled dynamically based on package C states,
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* user space can't make reliable use of the CRCs, so let's just
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* completely disable it.
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*/
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pipe_config->ips_force_disable = enable;
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}
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if (IS_HASWELL(dev_priv)) {
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pipe_config->pch_pfit.force_thru = enable;
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if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
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pipe_config->pch_pfit.enabled != enable)
|
||
|
|
pipe_config->base.connectors_changed = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = drm_atomic_commit(state);
|
||
|
|
|
||
|
|
put_state:
|
||
|
|
if (ret == -EDEADLK) {
|
||
|
|
drm_atomic_state_clear(state);
|
||
|
|
drm_modeset_backoff(&ctx);
|
||
|
|
goto retry;
|
||
|
|
}
|
||
|
|
|
||
|
|
drm_atomic_state_put(state);
|
||
|
|
unlock:
|
||
|
|
WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
|
||
|
|
drm_modeset_drop_locks(&ctx);
|
||
|
|
drm_modeset_acquire_fini(&ctx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
||
|
|
enum pipe pipe,
|
||
|
|
enum intel_pipe_crc_source *source,
|
||
|
|
uint32_t *val,
|
||
|
|
bool set_wa)
|
||
|
|
{
|
||
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
||
|
|
*source = INTEL_PIPE_CRC_SOURCE_PF;
|
||
|
|
|
||
|
|
switch (*source) {
|
||
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
||
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
|
||
|
|
break;
|
||
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
||
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
|
||
|
|
break;
|
||
|
|
case INTEL_PIPE_CRC_SOURCE_PF:
|
||
|
|
if (set_wa && (IS_HASWELL(dev_priv) ||
|
||
|
|
IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
|
||
|
|
hsw_pipe_A_crc_wa(dev_priv, true);
|
||
|
|
|
||
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
|
||
|
|
break;
|
||
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
||
|
|
*val = 0;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
||
|
|
enum pipe pipe,
|
||
|
|
enum intel_pipe_crc_source *source, u32 *val,
|
||
|
|
bool set_wa)
|
||
|
|
{
|
||
|
|
if (IS_GEN2(dev_priv))
|
||
|
|
return i8xx_pipe_crc_ctl_reg(source, val);
|
||
|
|
else if (INTEL_GEN(dev_priv) < 5)
|
||
|
|
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
||
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||
|
|
return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
||
|
|
else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
|
||
|
|
return ilk_pipe_crc_ctl_reg(source, val);
|
||
|
|
else
|
||
|
|
return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (!buf) {
|
||
|
|
*s = INTEL_PIPE_CRC_SOURCE_NONE;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
|
||
|
|
if (i < 0)
|
||
|
|
return i;
|
||
|
|
|
||
|
|
*s = i;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_display_crc_init(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
enum pipe pipe;
|
||
|
|
|
||
|
|
for_each_pipe(dev_priv, pipe) {
|
||
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
||
|
|
|
||
|
|
spin_lock_init(&pipe_crc->lock);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
|
||
|
|
size_t *values_cnt)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
||
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
||
|
|
enum intel_display_power_domain power_domain;
|
||
|
|
enum intel_pipe_crc_source source;
|
||
|
|
u32 val = 0; /* shut up gcc */
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (display_crc_ctl_parse_source(source_name, &source) < 0) {
|
||
|
|
DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
power_domain = POWER_DOMAIN_PIPE(crtc->index);
|
||
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
|
||
|
|
DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
|
||
|
|
return -EIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
|
||
|
|
if (ret != 0)
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
pipe_crc->source = source;
|
||
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
|
||
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
||
|
|
|
||
|
|
if (!source) {
|
||
|
|
if (IS_G4X(dev_priv))
|
||
|
|
g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
|
||
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||
|
|
vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
|
||
|
|
else if ((IS_HASWELL(dev_priv) ||
|
||
|
|
IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
|
||
|
|
hsw_pipe_A_crc_wa(dev_priv, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
pipe_crc->skipped = 0;
|
||
|
|
*values_cnt = 5;
|
||
|
|
|
||
|
|
out:
|
||
|
|
intel_display_power_put(dev_priv, power_domain);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
|
||
|
|
{
|
||
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
||
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
||
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
||
|
|
u32 val = 0;
|
||
|
|
|
||
|
|
if (!crtc->crc.opened)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* Don't need pipe_crc->lock here, IRQs are not generated. */
|
||
|
|
pipe_crc->skipped = 0;
|
||
|
|
|
||
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
|
||
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
|
||
|
|
{
|
||
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
||
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
||
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
||
|
|
|
||
|
|
/* Swallow crc's until we stop generating them. */
|
||
|
|
spin_lock_irq(&pipe_crc->lock);
|
||
|
|
pipe_crc->skipped = INT_MIN;
|
||
|
|
spin_unlock_irq(&pipe_crc->lock);
|
||
|
|
|
||
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
|
||
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
||
|
|
synchronize_irq(dev_priv->drm.irq);
|
||
|
|
}
|