351 lines
8.8 KiB
C
351 lines
8.8 KiB
C
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/gpuobj.h>
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#include <core/memory.h>
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#include <subdev/timer.h>
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static void
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nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
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u32 size, u16 tag, u8 port, bool secure)
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{
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u8 rem = size % 4;
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u32 reg;
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int i;
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size -= rem;
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reg = start | BIT(24) | (secure ? BIT(28) : 0);
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nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg);
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for (i = 0; i < size / 4; i++) {
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/* write new tag every 256B */
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if ((i & 0x3f) == 0)
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nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]);
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}
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/*
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* If size is not a multiple of 4, mask the last work to ensure garbage
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* does not get written
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*/
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if (rem) {
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u32 extra = ((u32 *)data)[i];
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/* write new tag every 256B */
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if ((i & 0x3f) == 0)
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nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16),
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extra & (BIT(rem * 8) - 1));
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++i;
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}
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/* code must be padded to 0x40 words */
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for (; i & 0x3f; i++)
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0);
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}
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static void
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nvkm_falcon_v1_load_emem(struct nvkm_falcon *falcon, void *data, u32 start,
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u32 size, u8 port)
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{
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u8 rem = size % 4;
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int i;
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size -= rem;
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nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 24));
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for (i = 0; i < size / 4; i++)
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nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), ((u32 *)data)[i]);
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/*
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* If size is not a multiple of 4, mask the last word to ensure garbage
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* does not get written
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*/
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if (rem) {
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u32 extra = ((u32 *)data)[i];
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nvkm_falcon_wr32(falcon, 0xac4 + (port * 8),
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extra & (BIT(rem * 8) - 1));
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}
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}
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static const u32 EMEM_START_ADDR = 0x1000000;
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static void
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nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
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u32 size, u8 port)
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{
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u8 rem = size % 4;
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int i;
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if (start >= EMEM_START_ADDR && falcon->has_emem)
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return nvkm_falcon_v1_load_emem(falcon, data,
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start - EMEM_START_ADDR, size,
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port);
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size -= rem;
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nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24));
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for (i = 0; i < size / 4; i++)
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nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]);
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/*
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* If size is not a multiple of 4, mask the last word to ensure garbage
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* does not get written
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*/
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if (rem) {
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u32 extra = ((u32 *)data)[i];
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nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8),
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extra & (BIT(rem * 8) - 1));
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}
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}
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static void
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nvkm_falcon_v1_read_emem(struct nvkm_falcon *falcon, u32 start, u32 size,
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u8 port, void *data)
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{
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u8 rem = size % 4;
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int i;
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size -= rem;
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nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 25));
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for (i = 0; i < size / 4; i++)
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((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));
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/*
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* If size is not a multiple of 4, mask the last word to ensure garbage
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* does not get read
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*/
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if (rem) {
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u32 extra = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));
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for (i = size; i < size + rem; i++) {
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((u8 *)data)[i] = (u8)(extra & 0xff);
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extra >>= 8;
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}
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}
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}
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static void
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nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size,
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u8 port, void *data)
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{
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u8 rem = size % 4;
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int i;
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if (start >= EMEM_START_ADDR && falcon->has_emem)
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return nvkm_falcon_v1_read_emem(falcon, start - EMEM_START_ADDR,
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size, port, data);
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size -= rem;
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nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 25));
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for (i = 0; i < size / 4; i++)
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((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));
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/*
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* If size is not a multiple of 4, mask the last word to ensure garbage
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* does not get read
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*/
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if (rem) {
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u32 extra = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));
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for (i = size; i < size + rem; i++) {
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((u8 *)data)[i] = (u8)(extra & 0xff);
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extra >>= 8;
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}
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}
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}
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static void
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nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx)
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{
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u32 inst_loc;
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u32 fbif;
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/* disable instance block binding */
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if (ctx == NULL) {
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nvkm_falcon_wr32(falcon, 0x10c, 0x0);
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return;
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}
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switch (falcon->owner->index) {
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case NVKM_ENGINE_NVENC0:
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case NVKM_ENGINE_NVENC1:
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case NVKM_ENGINE_NVENC2:
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fbif = 0x800;
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break;
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case NVKM_SUBDEV_PMU:
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fbif = 0xe00;
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break;
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default:
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fbif = 0x600;
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break;
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}
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nvkm_falcon_wr32(falcon, 0x10c, 0x1);
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/* setup apertures - virtual */
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nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_UCODE, 0x4);
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nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_VIRT, 0x0);
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/* setup apertures - physical */
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nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_VID, 0x4);
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nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5);
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nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6);
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/* Set context */
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switch (nvkm_memory_target(ctx)) {
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case NVKM_MEM_TARGET_VRAM: inst_loc = 0; break;
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case NVKM_MEM_TARGET_HOST: inst_loc = 2; break;
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case NVKM_MEM_TARGET_NCOH: inst_loc = 3; break;
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default:
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WARN_ON(1);
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return;
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}
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/* Enable context */
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nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1);
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nvkm_falcon_wr32(falcon, 0x054,
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((nvkm_memory_addr(ctx) >> 12) & 0xfffffff) |
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(inst_loc << 28) | (1 << 30));
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nvkm_falcon_mask(falcon, 0x090, 0x10000, 0x10000);
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nvkm_falcon_mask(falcon, 0x0a4, 0x8, 0x8);
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}
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static void
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nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr)
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{
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nvkm_falcon_wr32(falcon, 0x104, start_addr);
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}
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static void
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nvkm_falcon_v1_start(struct nvkm_falcon *falcon)
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{
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u32 reg = nvkm_falcon_rd32(falcon, 0x100);
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if (reg & BIT(6))
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nvkm_falcon_wr32(falcon, 0x130, 0x2);
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else
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nvkm_falcon_wr32(falcon, 0x100, 0x2);
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}
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static int
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nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms)
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{
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struct nvkm_device *device = falcon->owner->device;
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int ret;
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ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int
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nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask)
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{
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struct nvkm_device *device = falcon->owner->device;
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int ret;
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/* clear interrupt(s) */
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nvkm_falcon_mask(falcon, 0x004, mask, mask);
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/* wait until interrupts are cleared */
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ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int
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falcon_v1_wait_idle(struct nvkm_falcon *falcon)
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{
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struct nvkm_device *device = falcon->owner->device;
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int ret;
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ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int
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nvkm_falcon_v1_enable(struct nvkm_falcon *falcon)
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{
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struct nvkm_device *device = falcon->owner->device;
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int ret;
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ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0);
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if (ret < 0) {
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nvkm_error(falcon->user, "Falcon mem scrubbing timeout\n");
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return ret;
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}
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ret = falcon_v1_wait_idle(falcon);
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if (ret)
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return ret;
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/* enable IRQs */
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nvkm_falcon_wr32(falcon, 0x010, 0xff);
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return 0;
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}
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static void
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nvkm_falcon_v1_disable(struct nvkm_falcon *falcon)
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{
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/* disable IRQs and wait for any previous code to complete */
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nvkm_falcon_wr32(falcon, 0x014, 0xff);
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falcon_v1_wait_idle(falcon);
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}
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static const struct nvkm_falcon_func
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nvkm_falcon_v1 = {
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.load_imem = nvkm_falcon_v1_load_imem,
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.load_dmem = nvkm_falcon_v1_load_dmem,
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.read_dmem = nvkm_falcon_v1_read_dmem,
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.bind_context = nvkm_falcon_v1_bind_context,
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.start = nvkm_falcon_v1_start,
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.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
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.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
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.enable = nvkm_falcon_v1_enable,
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.disable = nvkm_falcon_v1_disable,
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.set_start_addr = nvkm_falcon_v1_set_start_addr,
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};
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int
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nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
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struct nvkm_falcon **pfalcon)
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{
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struct nvkm_falcon *falcon;
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if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon);
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return 0;
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}
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