352 lines
10 KiB
C
352 lines
10 KiB
C
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#ifndef __SM5714_MUIC_H__
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#define __SM5714_MUIC_H__
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/*
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* Copyright (C) 2015 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/muic/muic.h>
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#if defined(CONFIG_IF_CB_MANAGER)
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#include <linux/usb/typec/manager/if_cb_manager.h>
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#endif
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#define MUIC_DEV_NAME "muic-sm5714"
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/* SM5714 muic register read/write related information defines. */
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/* SM5714 Control register */
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#define CTRL_nSW_OPEN_SHIFT 5
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#define CTRL_DCDTIMER_SHIFT 3
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#define CTRL_ENDCDTIMER_SHIFT 2
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#define CTRL_BC12OFF_SHIFT 1
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#define CTRL_BCD_RESCAN_SHIFT 0
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#define CTRL_nSW_OPEN_MASK (0x1 << CTRL_nSW_OPEN_SHIFT)
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#define CTRL_DCDTIMER_MASK (0x3 << CTRL_DCDTIMER_SHIFT)
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#define CTRL_ENDCDTIMER_MASK (0x1 << CTRL_ENDCDTIMER_SHIFT)
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#define CTRL_BC12OFF_MASK (0x1 << CTRL_BC12OFF_SHIFT)
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#define CTRL_BCD_RESCAN_MASK (0x1 << CTRL_BCD_RESCAN_SHIFT)
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/* SM5714 MUIC Interrupt 1 register */
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#define INT1_DPDM_OVP_SHIFT 5
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#define INT1_VBUS_RID_DETACH_SHIFT 4
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#define INT1_RID_DETECT_SHIFT 2
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#define INT1_CHGTYPE_SHIFT 1
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#define INT1_DCDTIMEOUT_SHIFT 0
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#define INT1_DPDM_OVP_MASK (0x1 << INT1_DPDM_OVP_SHIFT)
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#define INT1_VBUS_RID_DETACH_MASK (0x1 << INT1_VBUS_RID_DETACH_SHIFT)
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#define INT1_RID_DETECT_MASK (0x1 << INT1_RID_DETECT_SHIFT)
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#define INT1_CHGTYPE_MASK (0x1 << INT1_CHGTYPE_SHIFT)
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#define INT1_DCDTIMEOUT_MASK (0x1 << INT1_DCDTIMEOUT_SHIFT)
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/* SM5714 MUIC Interrupt 2 register */
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#define INT2_AFC_ERROR_SHIFT 5
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#define INT2_AFC_STA_CHG_SHIFT 4
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#define INT2_MULTI_BYTE_SHIFT 3
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#define INT2_VBUS_UPDATE_SHIFT 2
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#define INT2_AFC_ACCEPTED_SHIFT 1
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#define INT2_AFC_TA_ATTACHED_SHIFT 0
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#define INT2_AFC_ERROR_MASK (0x1 << INT2_AFC_ERROR_SHIFT)
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#define INT2_AFC_STA_CHG_MASK (0x1 << INT2_AFC_STA_CHG_SHIFT)
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#define INT2_MULTI_BYTE_MASK (0x1 << INT2_MULTI_BYTE_SHIFT)
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#define INT2_VBUS_UPDATE_MASK (0x1 << INT2_VBUS_UPDATE_SHIFT)
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#define INT2_AFC_ACCEPTED_MASK (0x1 << INT2_AFC_ACCEPTED_SHIFT)
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#define INT2_AFC_TA_ATTACHED_MASK (0x1 << INT2_AFC_TA_ATTACHED_SHIFT)
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#define SM5714_MUIC_IRQ_PROBE (-1)
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#define SM5714_MUIC_IRQ_WORK (-2)
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/* SM5714 MUIC Device Type 1 register */
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#define DEV_TYPE1_LO_TA (0x1 << 7)
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#define DEV_TYPE1_QC20_TA (0x1 << 6)
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#define DEV_TYPE1_AFC_TA (0x1 << 5)
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#define DEV_TYPE1_U200 (0x1 << 4)
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#define DEV_TYPE1_CDP (0x1 << 3)
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#define DEV_TYPE1_DCP (0x1 << 2)
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#define DEV_TYPE1_SDP (0x1 << 1)
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#define DEV_TYPE1_DCD_OUT_SDP (0x1 << 0)
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#define DEV_TYPE1_USB_TYPES (DEV_TYPE1_CDP | DEV_TYPE1_SDP)
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#define DEV_TYPE1_CHG_TYPES (DEV_TYPE1_DCP | DEV_TYPE1_CDP \
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| DEV_TYPE1_U200)
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#define DEV_TYPE1_AFC_DCP (DEV_TYPE1_DCP | DEV_TYPE1_AFC_TA)
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#define DEV_TYPE1_QC20_DCP (DEV_TYPE1_DCP | DEV_TYPE1_QC20_TA)
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/* SM5714 MUIC Device Type 2 register */
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#define DEV_TYPE2_DEBUG_JTAG (0x1 << 7)
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#define DEV_TYPE2_HVDCP (0x1 << 6)
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#define DEV_TYPE2_JIG_UART_OFF (0x1 << 3)
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#define DEV_TYPE2_JIG_UART_ON (0x1 << 2)
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#define DEV_TYPE2_JIG_USB_OFF (0x1 << 1)
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#define DEV_TYPE2_JIG_USB_ON (0x1 << 0)
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#define DEV_TYPE2_JIG_USB_TYPES (DEV_TYPE2_JIG_USB_OFF \
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| DEV_TYPE2_JIG_USB_ON)
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#define DEV_TYPE2_JIG_UART_TYPES (DEV_TYPE2_JIG_UART_OFF)
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#define DEV_TYPE2_JIG_TYPES (DEV_TYPE2_JIG_UART_TYPES \
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| DEV_TYPE2_JIG_USB_TYPES)
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/* SM5714 AFC CTRL register */
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#define AFCCTRL_QC20_9V 6
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#define AFCCTRL_DIS_AFC 5
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#define AFCCTRL_HVDCPTIMER 4
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#define AFCCTRL_VBUS_READ 3
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#define AFCCTRL_DM_RESET 2
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#define AFCCTRL_DP_RESET 1
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#define AFCCTRL_ENAFC 0
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/*
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* Manual Switch
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* D- [5:3] / D+ [2:0]
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* 000: Open all / 001: USB / 010: JTGA / 011: UART / 100: GND
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*/
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#define MANUAL_SW_DM_SHIFT 3
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#define MANUAL_SW_DP_SHIFT 0
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#define MANUAL_SW_OPEN (0x0)
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#define MANUAL_SW_USB (0x1 << MANUAL_SW_DM_SHIFT \
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| 0x1 << MANUAL_SW_DP_SHIFT)
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#define MANUAL_SW_JTAG (0x2 << MANUAL_SW_DM_SHIFT \
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| 0x2 << MANUAL_SW_DP_SHIFT)
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#define MANUAL_SW_UART (0x3 << MANUAL_SW_DM_SHIFT \
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| 0x3 << MANUAL_SW_DP_SHIFT)
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#define MANUAL_SW_HICCUP (0x4 << MANUAL_SW_DM_SHIFT \
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| 0x4 << MANUAL_SW_DP_SHIFT)
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enum sm5714_reg_manual_sw_value {
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MANSW_OPEN = (MANUAL_SW_OPEN),
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MANSW_USB = (MANUAL_SW_USB),
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MANSW_JTAG = (MANUAL_SW_JTAG),
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MANSW_OTG = (MANUAL_SW_USB),
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MANSW_UART = (MANUAL_SW_UART),
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MANSW_HICCUP = (MANUAL_SW_HICCUP),
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MANSW_OPEN_RUSTPROOF = (MANUAL_SW_OPEN),
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};
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#define MANSW_AUTOMATIC 0
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#define MANSW_MANUAL 1
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#define AFC_TXBYTE_5V 0x0
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#define AFC_TXBYTE_6V 0x1
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#define AFC_TXBYTE_7V 0x2
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#define AFC_TXBYTE_8V 0x3
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#define AFC_TXBYTE_9V 0x4
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#define AFC_TXBYTE_10V 0x5
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#define AFC_TXBYTE_11V 0x6
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#define AFC_TXBYTE_12V 0x7
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#define AFC_TXBYTE_13V 0x8
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#define AFC_TXBYTE_14V 0x9
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#define AFC_TXBYTE_15V 0xA
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#define AFC_TXBYTE_16V 0xB
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#define AFC_TXBYTE_17V 0xC
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#define AFC_TXBYTE_18V 0xD
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#define AFC_TXBYTE_19V 0xE
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#define AFC_TXBYTE_20V 0xF
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#define AFC_TXBYTE_0_75A 0x0
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#define AFC_TXBYTE_0_90A 0x1
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#define AFC_TXBYTE_1_05A 0x2
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#define AFC_TXBYTE_1_20A 0x3
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#define AFC_TXBYTE_1_35A 0x4
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#define AFC_TXBYTE_1_50A 0x5
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#define AFC_TXBYTE_1_65A 0x6
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#define AFC_TXBYTE_1_80A 0x7
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#define AFC_TXBYTE_1_95A 0x8
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#define AFC_TXBYTE_2_10A 0x9
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#define AFC_TXBYTE_2_25A 0xA
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#define AFC_TXBYTE_2_40A 0xB
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#define AFC_TXBYTE_2_55A 0xC
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#define AFC_TXBYTE_2_70A 0xD
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#define AFC_TXBYTE_2_85A 0xE
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#define AFC_TXBYTE_3_00A 0xF
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#define AFC_TXBYTE_5V_1_95A ((AFC_TXBYTE_5V << 4) | AFC_TXBYTE_1_95A)
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#define AFC_TXBYTE_9V_1_65A ((AFC_TXBYTE_9V << 4) | AFC_TXBYTE_1_65A)
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#define AFC_TXBYTE_12V_2_10A ((AFC_TXBYTE_12V << 4) | AFC_TXBYTE_2_10A)
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#define SM5714_MUIC_AFC_TA 0x00
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#define SM5714_MUIC_QC20 0x01
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#define SM5714_MUIC_HV_5V 0x08
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#define SM5714_MUIC_HV_9V 0x46
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#define SM5714_MUIC_HV_12V 0x79
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#define SM5714_ENQC20_5V 0x0
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#define SM5714_ENQC20_9V 0x1
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#define SM5714_ENQC20_12V 0x2
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#define SM5714_MUIC_REG_CFG1 0x31
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#define SM5714_MUIC_REG_CFG2 0x32
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#define SM5714_MUIC_REG_USBKS 0x38
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#define SM5714_MUIC_REG_VBUS 0x3B
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#define SM5714_MUIC_REG_AFC_RX_NUM 0x3D
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#define SM5714_MUIC_REG_AFC_RX_P0 0x3E
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#define SM5714_MUIC_REG_AFC_RX_P1 0x3F
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#define SM5714_MUIC_REG_BCD_STATE 0x42
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#define SM5714_MUIC_REG_AFC_STATE 0x43
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#define SM5714_MUIC_REG_OTP_IF_STS 0x58
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struct sm5714_muic_irq_t {
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/* int1 */
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int irq_dpdm_ovp;
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int irq_vbus_rid_detach;
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int irq_rid_detect;
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int irq_chgtype_attach;
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int irq_dectimeout;
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/* int2 */
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int irq_afc_error;
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int irq_afc_sta_chg;
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int irq_multi_byte;
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int irq_afc_accepted;
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int irq_afc_ta_attached;
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};
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#if defined(CONFIG_MUIC_SUPPORT_PDIC)
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enum {
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SM5714_MUIC_AFC_NORMAL = 0,
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SM5714_MUIC_AFC_ABNORMAL = 1,
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};
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#define MUIC_PDIC_NOTI_ATTACH (1)
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#define MUIC_PDIC_NOTI_DETACH (-1)
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#define MUIC_PDIC_NOTI_UNDEFINED (0)
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struct sm5714_pdic_evt {
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int pdic_evt_attached; /* 1: attached, -1: detached, 0: undefined */
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int pdic_evt_rid; /* the last rid */
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int pdic_evt_rprd; /*rprd */
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int pdic_evt_roleswap; /* check rprd role swap event */
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int pdic_evt_dcdcnt; /* count dcd timeout */
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int pdic_evt_abnormal_sbu_short_gender; /* sbu short gender */
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};
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#endif
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struct sm5714_muic_data {
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struct device *dev;
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struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
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struct mutex muic_mutex;
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/* model dependant muic platform data */
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struct muic_platform_data *pdata;
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void *muic_data;
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/* muic current attached device */
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muic_attached_dev_t attached_dev;
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/*struct muic_intr_data intr;*/
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struct sm5714_muic_irq_t irqs;
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int gpio_uart_sel;
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/* muic Device ID */
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u8 muic_vendor; /* Vendor ID */
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u8 muic_version; /* Version ID */
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bool is_factory_start;
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bool is_rustproof;
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bool is_otg_test;
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#if defined(CONFIG_USB_EXTERNAL_NOTIFY)
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/* USB Notifier */
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struct notifier_block usb_nb;
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#endif
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#if defined(CONFIG_MUIC_SUPPORT_PDIC)
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struct sm5714_pdic_evt pdic_info_data;
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int pdic_evt_id;
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bool need_to_path_open;
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#ifdef CONFIG_USB_TYPEC_MANAGER_NOTIFIER
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struct notifier_block manager_nb;
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#else
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struct notifier_block pdic_nb;
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#endif
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#ifdef CONFIG_VBUS_NOTIFIER
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struct notifier_block vbus_nb;
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#endif
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int pdic_afc_state;
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int pdic_afc_state_count;
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struct delayed_work pdic_afc_work;
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#endif
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struct mutex afc_mutex;
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struct sm5714_dev *sm5714_dev;
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/* model dependant mfd platform data */
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struct sm5714_platform_data *mfd_pdata;
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int dev1;
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int dev2;
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struct wake_lock wake_lock;
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bool suspended;
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bool need_to_noti;
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bool is_water_detect;
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int vbus_state;
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/* AFC */
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bool afc_irq_disabled;
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int afc_retry_count;
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int vbus_changed_9to5;
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int fled_torch_enable;
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int fled_flash_enable;
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struct delayed_work afc_retry_work;
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struct delayed_work afc_torch_work;
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struct work_struct muic_afc_init_work;
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struct work_struct muic_event_work;
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struct delayed_work muic_debug_work;
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#if defined(CONFIG_IF_CB_MANAGER)
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struct muic_dev *muic_d;
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struct if_cb_manager *man;
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#endif
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#if defined(CONFIG_HICCUP_CHARGER)
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bool is_hiccup_mode;
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#endif
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};
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extern struct device *switch_device;
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extern unsigned int system_rev;
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extern struct muic_platform_data muic_pdata;
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int sm5714_i2c_read_byte(struct i2c_client *client, u8 command);
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int sm5714_i2c_write_byte(struct i2c_client *client, u8 command, u8 value);
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int muic_request_disable_afc_state(void);
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int muic_check_fled_state(int enable, int mode);
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int muic_disable_afc(int disable);
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int sm5714_muic_voltage_control(struct sm5714_muic_data *muic_data, int afctxd, int qc20);
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int sm5714_muic_afc_set_voltage(int vol);
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int sm5714_muic_charger_init(void);
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int sm5714_afc_ta_attach(struct sm5714_muic_data *muic_data);
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int sm5714_afc_ta_accept(struct sm5714_muic_data *muic_data);
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int sm5714_afc_multi_byte(struct sm5714_muic_data *muic_data);
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int sm5714_afc_error(struct sm5714_muic_data *muic_data);
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int sm5714_afc_sta_chg(struct sm5714_muic_data *muic_data);
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int sm5714_muic_get_vbus_value(struct sm5714_muic_data *muic_data);
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int sm5714_set_afc_ctrl_reg(struct sm5714_muic_data *muic_data,
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int shift, bool on);
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void sm5714_hv_muic_initialize(struct sm5714_muic_data *muic_data);
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#if defined(CONFIG_MUIC_SUPPORT_PDIC)
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void sm5714_muic_register_pdic_notifier(struct sm5714_muic_data *pmuic);
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void sm5714_muic_unregister_pdic_notifier(struct sm5714_muic_data *pmuic);
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#endif
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#endif /* __SM5714_MUIC_H__ */
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