55 lines
2 KiB
ReStructuredText
55 lines
2 KiB
ReStructuredText
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Introduction
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============
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The FPGA subsystem supports reprogramming FPGAs dynamically under
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Linux. Some of the core intentions of the FPGA subsystems are:
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* The FPGA subsystem is vendor agnostic.
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* The FPGA subsystem separates upper layers (userspace interfaces and
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enumeration) from lower layers that know how to program a specific
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FPGA.
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* Code should not be shared between upper and lower layers. This
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should go without saying. If that seems necessary, there's probably
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framework functionality that can be added that will benefit
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other users. Write the linux-fpga mailing list and maintainers and
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seek out a solution that expands the framework for broad reuse.
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* Generally, when adding code, think of the future. Plan for reuse.
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The framework in the kernel is divided into:
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FPGA Manager
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------------
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If you are adding a new FPGA or a new method of programming an FPGA,
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this is the subsystem for you. Low level FPGA manager drivers contain
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the knowledge of how to program a specific device. This subsystem
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includes the framework in fpga-mgr.c and the low level drivers that
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are registered with it.
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FPGA Bridge
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-----------
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FPGA Bridges prevent spurious signals from going out of an FPGA or a
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region of an FPGA during programming. They are disabled before
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programming begins and re-enabled afterwards. An FPGA bridge may be
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actual hard hardware that gates a bus to a CPU or a soft ("freeze")
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bridge in FPGA fabric that surrounds a partial reconfiguration region
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of an FPGA. This subsystem includes fpga-bridge.c and the low level
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drivers that are registered with it.
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FPGA Region
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-----------
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If you are adding a new interface to the FPGA framework, add it on top
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of an FPGA region to allow the most reuse of your interface.
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The FPGA Region framework (fpga-region.c) associates managers and
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bridges as reconfigurable regions. A region may refer to the whole
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FPGA in full reconfiguration or to a partial reconfiguration region.
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The Device Tree FPGA Region support (of-fpga-region.c) handles
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reprogramming FPGAs when device tree overlays are applied.
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