348 lines
8.2 KiB
Plaintext
348 lines
8.2 KiB
Plaintext
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/*
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* wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* Licensed under GPLv2 or later
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "wm,wm8750";
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm1176jzf";
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&intc0>;
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intc0: interrupt-controller@d8140000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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reg = <0xd8140000 0x10000>;
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#interrupt-cells = <1>;
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};
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/* Secondary IC cascaded to intc0 */
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intc1: interrupt-controller@d8150000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xD8150000 0x10000>;
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interrupts = <56 57 58 59 60 61 62 63>;
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};
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pinctrl: pinctrl@d8110000 {
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compatible = "wm,wm8750-pinctrl";
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reg = <0xd8110000 0x10000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pmc@d8130000 {
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compatible = "via,vt8500-pmc";
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reg = <0xd8130000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ref24: ref24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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ref25: ref25M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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plla: plla {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x200>;
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};
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pllb: pllb {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x204>;
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};
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pllc: pllc {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x208>;
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};
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plld: plld {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x20C>;
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};
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plle: plle {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x210>;
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};
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clkarm: arm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plla>;
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divisor-reg = <0x300>;
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};
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clkahb: ahb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x304>;
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};
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clkapb: apb {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x320>;
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};
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clkddr: ddr {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plld>;
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divisor-reg = <0x310>;
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};
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <24>;
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};
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clkuart1: uart1 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <25>;
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};
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clkuart2: uart2 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <26>;
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};
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clkuart3: uart3 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <27>;
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};
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clkuart4: uart4 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <28>;
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};
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clkuart5: uart5 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <29>;
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};
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clkpwm: pwm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x350>;
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enable-reg = <0x250>;
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enable-bit = <17>;
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};
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clksdhc: sdhc {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x330>;
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divisor-mask = <0x3f>;
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enable-reg = <0x250>;
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enable-bit = <0>;
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};
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clki2c0: i2c0clk {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x3A0>;
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enable-reg = <0x250>;
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enable-bit = <8>;
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};
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clki2c1: i2c1clk {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x3A4>;
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enable-reg = <0x250>;
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enable-bit = <9>;
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};
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};
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};
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pwm: pwm@d8220000 {
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#pwm-cells = <3>;
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compatible = "via,vt8500-pwm";
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reg = <0xd8220000 0x100>;
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clocks = <&clkpwm>;
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};
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timer@d8130100 {
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compatible = "via,vt8500-timer";
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reg = <0xd8130100 0x28>;
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interrupts = <36>;
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};
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ehci@d8007900 {
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compatible = "via,vt8500-ehci";
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reg = <0xd8007900 0x200>;
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interrupts = <26>;
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};
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uhci@d8007b00 {
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compatible = "platform-uhci";
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reg = <0xd8007b00 0x200>;
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interrupts = <26>;
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};
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uhci@d8008d00 {
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compatible = "platform-uhci";
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reg = <0xd8008d00 0x200>;
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interrupts = <26>;
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};
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uart0: serial@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
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status = "disabled";
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};
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uart1: serial@d82b0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82b0000 0x1040>;
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interrupts = <33>;
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clocks = <&clkuart1>;
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status = "disabled";
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};
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uart2: serial@d8210000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8210000 0x1040>;
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interrupts = <47>;
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clocks = <&clkuart2>;
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status = "disabled";
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};
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uart3: serial@d82c0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82c0000 0x1040>;
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interrupts = <50>;
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clocks = <&clkuart3>;
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status = "disabled";
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};
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uart4: serial@d8370000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8370000 0x1040>;
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interrupts = <30>;
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clocks = <&clkuart4>;
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status = "disabled";
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};
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uart5: serial@d8380000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8380000 0x1040>;
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interrupts = <43>;
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clocks = <&clkuart5>;
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status = "disabled";
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};
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rtc@d8100000 {
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compatible = "via,vt8500-rtc";
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reg = <0xd8100000 0x10000>;
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interrupts = <48>;
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};
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sdhc@d800a000 {
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compatible = "wm,wm8505-sdhc";
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reg = <0xd800a000 0x1000>;
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interrupts = <20 21>;
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clocks = <&clksdhc>;
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bus-width = <4>;
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sdon-inverted;
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};
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i2c_0: i2c@d8280000 {
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compatible = "wm,wm8505-i2c";
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reg = <0xd8280000 0x1000>;
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interrupts = <19>;
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clocks = <&clki2c0>;
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clock-frequency = <400000>;
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};
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i2c_1: i2c@d8320000 {
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compatible = "wm,wm8505-i2c";
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reg = <0xd8320000 0x1000>;
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interrupts = <18>;
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clocks = <&clki2c1>;
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clock-frequency = <400000>;
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};
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};
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};
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