245 lines
7.1 KiB
C
245 lines
7.1 KiB
C
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/*
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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/slab.h>
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#include <linux/mman.h>
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#include <net/sock.h>
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#include "iw_cxgb4.h"
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static void print_tpte(struct c4iw_dev *dev, u32 stag)
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{
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int ret;
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struct fw_ri_tpte tpte;
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ret = cxgb4_read_tpte(dev->rdev.lldi.ports[0], stag,
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(__be32 *)&tpte);
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if (ret) {
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dev_err(&dev->rdev.lldi.pdev->dev,
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"%s cxgb4_read_tpte err %d\n", __func__, ret);
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return;
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}
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pr_debug("stag idx 0x%x valid %d key 0x%x state %d pdid %d perm 0x%x ps %d len 0x%llx va 0x%llx\n",
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stag & 0xffffff00,
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FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
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FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
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FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
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FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
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FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
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FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
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((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
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((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
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}
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static void dump_err_cqe(struct c4iw_dev *dev, struct t4_cqe *err_cqe)
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{
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__be64 *p = (void *)err_cqe;
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dev_err(&dev->rdev.lldi.pdev->dev,
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"AE qpid %d opcode %d status 0x%x "
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"type %d len 0x%x wrid.hi 0x%x wrid.lo 0x%x\n",
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CQE_QPID(err_cqe), CQE_OPCODE(err_cqe),
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CQE_STATUS(err_cqe), CQE_TYPE(err_cqe), ntohl(err_cqe->len),
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CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe));
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pr_debug("%016llx %016llx %016llx %016llx - %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(p[0]), be64_to_cpu(p[1]), be64_to_cpu(p[2]),
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be64_to_cpu(p[3]), be64_to_cpu(p[4]), be64_to_cpu(p[5]),
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be64_to_cpu(p[6]), be64_to_cpu(p[7]));
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/*
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* Ingress WRITE and READ_RESP errors provide
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* the offending stag, so parse and log it.
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*/
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if (RQ_TYPE(err_cqe) && (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE ||
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CQE_OPCODE(err_cqe) == FW_RI_READ_RESP))
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print_tpte(dev, CQE_WRID_STAG(err_cqe));
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}
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static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp,
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struct c4iw_qp *qhp,
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struct t4_cqe *err_cqe,
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enum ib_event_type ib_event)
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{
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struct ib_event event;
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struct c4iw_qp_attributes attrs;
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unsigned long flag;
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dump_err_cqe(dev, err_cqe);
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if (qhp->attr.state == C4IW_QP_STATE_RTS) {
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attrs.next_state = C4IW_QP_STATE_TERMINATE;
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c4iw_modify_qp(qhp->rhp, qhp, C4IW_QP_ATTR_NEXT_STATE,
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&attrs, 0);
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}
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event.event = ib_event;
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event.device = chp->ibcq.device;
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if (ib_event == IB_EVENT_CQ_ERR)
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event.element.cq = &chp->ibcq;
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else
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event.element.qp = &qhp->ibqp;
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if (qhp->ibqp.event_handler)
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(*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context);
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if (t4_clear_cq_armed(&chp->cq)) {
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spin_lock_irqsave(&chp->comp_handler_lock, flag);
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(*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
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spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
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}
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}
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void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe)
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{
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struct c4iw_cq *chp;
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struct c4iw_qp *qhp;
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u32 cqid;
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spin_lock_irq(&dev->lock);
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qhp = get_qhp(dev, CQE_QPID(err_cqe));
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if (!qhp) {
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pr_err("BAD AE qpid 0x%x opcode %d status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
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CQE_QPID(err_cqe),
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CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
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CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
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CQE_WRID_LOW(err_cqe));
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spin_unlock_irq(&dev->lock);
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goto out;
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}
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if (SQ_TYPE(err_cqe))
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cqid = qhp->attr.scq;
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else
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cqid = qhp->attr.rcq;
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chp = get_chp(dev, cqid);
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if (!chp) {
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pr_err("BAD AE cqid 0x%x qpid 0x%x opcode %d status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
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cqid, CQE_QPID(err_cqe),
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CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
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CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
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CQE_WRID_LOW(err_cqe));
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spin_unlock_irq(&dev->lock);
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goto out;
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}
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c4iw_qp_add_ref(&qhp->ibqp);
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atomic_inc(&chp->refcnt);
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spin_unlock_irq(&dev->lock);
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/* Bad incoming write */
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if (RQ_TYPE(err_cqe) &&
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(CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE)) {
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post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_REQ_ERR);
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goto done;
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}
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switch (CQE_STATUS(err_cqe)) {
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/* Completion Events */
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case T4_ERR_SUCCESS:
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pr_err("AE with status 0!\n");
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break;
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case T4_ERR_STAG:
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case T4_ERR_PDID:
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case T4_ERR_QPID:
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case T4_ERR_ACCESS:
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case T4_ERR_WRAP:
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case T4_ERR_BOUND:
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case T4_ERR_INVALIDATE_SHARED_MR:
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case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
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post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_ACCESS_ERR);
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break;
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/* Device Fatal Errors */
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case T4_ERR_ECC:
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case T4_ERR_ECC_PSTAG:
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case T4_ERR_INTERNAL_ERR:
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post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_DEVICE_FATAL);
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break;
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/* QP Fatal Errors */
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case T4_ERR_OUT_OF_RQE:
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case T4_ERR_PBL_ADDR_BOUND:
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case T4_ERR_CRC:
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case T4_ERR_MARKER:
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case T4_ERR_PDU_LEN_ERR:
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case T4_ERR_DDP_VERSION:
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case T4_ERR_RDMA_VERSION:
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case T4_ERR_OPCODE:
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case T4_ERR_DDP_QUEUE_NUM:
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case T4_ERR_MSN:
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case T4_ERR_TBIT:
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case T4_ERR_MO:
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case T4_ERR_MSN_GAP:
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case T4_ERR_MSN_RANGE:
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case T4_ERR_RQE_ADDR_BOUND:
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case T4_ERR_IRD_OVERFLOW:
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post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
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break;
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default:
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pr_err("Unknown T4 status 0x%x QPID 0x%x\n",
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CQE_STATUS(err_cqe), qhp->wq.sq.qid);
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post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
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break;
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}
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done:
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if (atomic_dec_and_test(&chp->refcnt))
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wake_up(&chp->wait);
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c4iw_qp_rem_ref(&qhp->ibqp);
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out:
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return;
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}
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int c4iw_ev_handler(struct c4iw_dev *dev, u32 qid)
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{
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struct c4iw_cq *chp;
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unsigned long flag;
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spin_lock_irqsave(&dev->lock, flag);
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chp = get_chp(dev, qid);
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if (chp) {
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atomic_inc(&chp->refcnt);
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spin_unlock_irqrestore(&dev->lock, flag);
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t4_clear_cq_armed(&chp->cq);
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spin_lock_irqsave(&chp->comp_handler_lock, flag);
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(*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
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spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
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if (atomic_dec_and_test(&chp->refcnt))
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wake_up(&chp->wait);
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} else {
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pr_debug("unknown cqid 0x%x\n", qid);
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spin_unlock_irqrestore(&dev->lock, flag);
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}
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return 0;
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}
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