366 lines
10 KiB
C
366 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cxd2880_tnrdmd.h
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* Sony CXD2880 DVB-T2/T tuner + demodulator driver
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* common control interface
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*
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* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
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*/
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#ifndef CXD2880_TNRDMD_H
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#define CXD2880_TNRDMD_H
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#include <linux/atomic.h>
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#include "cxd2880_common.h"
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#include "cxd2880_io.h"
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#include "cxd2880_dtv.h"
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#include "cxd2880_dvbt.h"
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#include "cxd2880_dvbt2.h"
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#define CXD2880_TNRDMD_MAX_CFG_MEM_COUNT 100
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#define slvt_unfreeze_reg(tnr_dmd) ((void)((tnr_dmd)->io->write_reg\
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((tnr_dmd)->io, CXD2880_IO_TGT_DMD, 0x01, 0x00)))
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_UNDERFLOW 0x0001
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_OVERFLOW 0x0002
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_EMPTY 0x0004
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_FULL 0x0008
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_RRDY 0x0010
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_COMMAND 0x0020
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_ACCESS 0x0040
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_CPU_ERROR 0x0100
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_LOCK 0x0200
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_INV_LOCK 0x0400
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_NOOFDM 0x0800
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_EWS 0x1000
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_EEW 0x2000
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_FEC_FAIL 0x4000
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_L1POST_OK 0x01
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_DMD_LOCK 0x02
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_TS_LOCK 0x04
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enum cxd2880_tnrdmd_chip_id {
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CXD2880_TNRDMD_CHIP_ID_UNKNOWN = 0x00,
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CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X = 0x62,
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CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11 = 0x6a
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};
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#define CXD2880_TNRDMD_CHIP_ID_VALID(chip_id) \
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(((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) || \
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((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11))
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enum cxd2880_tnrdmd_state {
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CXD2880_TNRDMD_STATE_UNKNOWN,
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CXD2880_TNRDMD_STATE_SLEEP,
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CXD2880_TNRDMD_STATE_ACTIVE,
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CXD2880_TNRDMD_STATE_INVALID
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};
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enum cxd2880_tnrdmd_divermode {
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CXD2880_TNRDMD_DIVERMODE_SINGLE,
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CXD2880_TNRDMD_DIVERMODE_MAIN,
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CXD2880_TNRDMD_DIVERMODE_SUB
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};
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enum cxd2880_tnrdmd_clockmode {
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CXD2880_TNRDMD_CLOCKMODE_UNKNOWN,
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CXD2880_TNRDMD_CLOCKMODE_A,
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CXD2880_TNRDMD_CLOCKMODE_B,
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CXD2880_TNRDMD_CLOCKMODE_C
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};
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enum cxd2880_tnrdmd_tsout_if {
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CXD2880_TNRDMD_TSOUT_IF_TS,
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CXD2880_TNRDMD_TSOUT_IF_SPI,
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CXD2880_TNRDMD_TSOUT_IF_SDIO
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};
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enum cxd2880_tnrdmd_xtal_share {
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CXD2880_TNRDMD_XTAL_SHARE_NONE,
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CXD2880_TNRDMD_XTAL_SHARE_EXTREF,
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CXD2880_TNRDMD_XTAL_SHARE_MASTER,
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CXD2880_TNRDMD_XTAL_SHARE_SLAVE
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};
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enum cxd2880_tnrdmd_spectrum_sense {
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CXD2880_TNRDMD_SPECTRUM_NORMAL,
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CXD2880_TNRDMD_SPECTRUM_INV
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};
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enum cxd2880_tnrdmd_cfg_id {
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CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB,
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CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE,
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CXD2880_TNRDMD_CFG_TSCLK_CONT,
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CXD2880_TNRDMD_CFG_TSCLK_MASK,
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CXD2880_TNRDMD_CFG_TSVALID_MASK,
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CXD2880_TNRDMD_CFG_TSERR_MASK,
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CXD2880_TNRDMD_CFG_TSERR_VALID_DIS,
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CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
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CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL,
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CXD2880_TNRDMD_CFG_TSPIN_PULLUP,
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CXD2880_TNRDMD_CFG_TSCLK_FREQ,
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CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL,
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CXD2880_TNRDMD_CFG_TS_PACKET_GAP,
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CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE,
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CXD2880_TNRDMD_CFG_PWM_VALUE,
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CXD2880_TNRDMD_CFG_INTERRUPT,
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CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL,
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CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL,
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CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS,
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CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS,
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CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS,
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CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE,
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CXD2880_TNRDMD_CFG_CABLE_INPUT,
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CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE,
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CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE,
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CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST,
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CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
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CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
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CXD2880_TNRDMD_CFG_DVBT_PER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
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};
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enum cxd2880_tnrdmd_lock_result {
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CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT,
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CXD2880_TNRDMD_LOCK_RESULT_LOCKED,
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CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED
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};
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enum cxd2880_tnrdmd_gpio_mode {
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CXD2880_TNRDMD_GPIO_MODE_OUTPUT = 0x00,
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CXD2880_TNRDMD_GPIO_MODE_INPUT = 0x01,
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CXD2880_TNRDMD_GPIO_MODE_INT = 0x02,
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CXD2880_TNRDMD_GPIO_MODE_FEC_FAIL = 0x03,
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CXD2880_TNRDMD_GPIO_MODE_PWM = 0x04,
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CXD2880_TNRDMD_GPIO_MODE_EWS = 0x05,
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CXD2880_TNRDMD_GPIO_MODE_EEW = 0x06
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};
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enum cxd2880_tnrdmd_serial_ts_clk {
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CXD2880_TNRDMD_SERIAL_TS_CLK_FULL,
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CXD2880_TNRDMD_SERIAL_TS_CLK_HALF
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};
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struct cxd2880_tnrdmd_cfg_mem {
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enum cxd2880_io_tgt tgt;
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u8 bank;
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u8 address;
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u8 value;
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u8 bit_mask;
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};
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struct cxd2880_tnrdmd_pid_cfg {
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u8 is_en;
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u16 pid;
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};
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struct cxd2880_tnrdmd_pid_ftr_cfg {
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u8 is_negative;
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struct cxd2880_tnrdmd_pid_cfg pid_cfg[32];
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};
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struct cxd2880_tnrdmd_lna_thrs {
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u8 off_on;
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u8 on_off;
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};
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struct cxd2880_tnrdmd_lna_thrs_tbl_air {
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struct cxd2880_tnrdmd_lna_thrs thrs[24];
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};
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struct cxd2880_tnrdmd_lna_thrs_tbl_cable {
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struct cxd2880_tnrdmd_lna_thrs thrs[32];
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};
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struct cxd2880_tnrdmd_create_param {
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enum cxd2880_tnrdmd_tsout_if ts_output_if;
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u8 en_internal_ldo;
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enum cxd2880_tnrdmd_xtal_share xtal_share_type;
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u8 xosc_cap;
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u8 xosc_i;
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u8 is_cxd2881gg;
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u8 stationary_use;
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};
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struct cxd2880_tnrdmd_diver_create_param {
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enum cxd2880_tnrdmd_tsout_if ts_output_if;
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u8 en_internal_ldo;
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u8 xosc_cap_main;
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u8 xosc_i_main;
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u8 xosc_i_sub;
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u8 is_cxd2881gg;
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u8 stationary_use;
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};
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struct cxd2880_tnrdmd {
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struct cxd2880_tnrdmd *diver_sub;
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struct cxd2880_io *io;
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struct cxd2880_tnrdmd_create_param create_param;
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enum cxd2880_tnrdmd_divermode diver_mode;
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enum cxd2880_tnrdmd_clockmode fixed_clk_mode;
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u8 is_cable_input;
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u8 en_fef_intmtnt_base;
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u8 en_fef_intmtnt_lite;
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u8 blind_tune_dvbt2_first;
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int (*rf_lvl_cmpstn)(struct cxd2880_tnrdmd *tnr_dmd,
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int *rf_lvl_db);
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struct cxd2880_tnrdmd_lna_thrs_tbl_air *lna_thrs_tbl_air;
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struct cxd2880_tnrdmd_lna_thrs_tbl_cable *lna_thrs_tbl_cable;
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u8 srl_ts_clk_mod_cnts;
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enum cxd2880_tnrdmd_serial_ts_clk srl_ts_clk_frq;
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u8 ts_byte_clk_manual_setting;
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u8 is_ts_backwards_compatible_mode;
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struct cxd2880_tnrdmd_cfg_mem cfg_mem[CXD2880_TNRDMD_MAX_CFG_MEM_COUNT];
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u8 cfg_mem_last_entry;
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struct cxd2880_tnrdmd_pid_ftr_cfg pid_ftr_cfg;
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u8 pid_ftr_cfg_en;
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void *user;
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enum cxd2880_tnrdmd_chip_id chip_id;
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enum cxd2880_tnrdmd_state state;
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enum cxd2880_tnrdmd_clockmode clk_mode;
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u32 frequency_khz;
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enum cxd2880_dtv_sys sys;
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enum cxd2880_dtv_bandwidth bandwidth;
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u8 scan_mode;
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atomic_t cancel;
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};
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int cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd,
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struct cxd2880_io *io,
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struct cxd2880_tnrdmd_create_param
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*create_param);
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int cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd
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*tnr_dmd_main,
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struct cxd2880_io *io_main,
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struct cxd2880_tnrdmd *tnr_dmd_sub,
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struct cxd2880_io *io_sub,
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struct
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cxd2880_tnrdmd_diver_create_param
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*create_param);
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int cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd
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*tnr_dmd,
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u8 *task_completed);
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int cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd
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*tnr_dmd,
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enum cxd2880_dtv_sys sys,
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u32 frequency_khz,
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enum cxd2880_dtv_bandwidth
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bandwidth, u8 one_seg_opt,
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u8 one_seg_opt_shft_dir);
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int cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd
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*tnr_dmd,
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enum cxd2880_dtv_sys sys,
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u8 en_fef_intmtnt_ctrl);
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int cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
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enum cxd2880_tnrdmd_cfg_id id,
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int value);
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int cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id,
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u8 en,
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enum cxd2880_tnrdmd_gpio_mode mode,
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u8 open_drain, u8 invert);
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int cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id,
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u8 en,
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enum cxd2880_tnrdmd_gpio_mode
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mode, u8 open_drain,
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u8 invert);
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int cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 *value);
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int cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 *value);
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int cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 value);
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int cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 value);
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int cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd,
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u16 *value);
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int cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd,
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||
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u16 value);
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||
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|
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||
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int cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd,
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||
|
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u8 clear_overflow_flag,
|
||
|
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u8 clear_underflow_flag,
|
||
|
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u8 clear_buf);
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||
|
|
|
||
|
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int cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd,
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||
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enum cxd2880_tnrdmd_chip_id *chip_id);
|
||
|
|
|
||
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int cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd
|
||
|
|
*tnr_dmd,
|
||
|
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enum cxd2880_io_tgt tgt,
|
||
|
|
u8 bank, u8 address,
|
||
|
|
u8 value, u8 bit_mask);
|
||
|
|
|
||
|
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int cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
enum cxd2880_dtv_sys sys,
|
||
|
|
u8 scan_mode_end);
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
struct cxd2880_tnrdmd_pid_ftr_cfg
|
||
|
|
*pid_ftr_cfg);
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd
|
||
|
|
*tnr_dmd,
|
||
|
|
int (*rf_lvl_cmpstn)
|
||
|
|
(struct cxd2880_tnrdmd *,
|
||
|
|
int *));
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
int (*rf_lvl_cmpstn)
|
||
|
|
(struct cxd2880_tnrdmd *,
|
||
|
|
int *));
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
struct
|
||
|
|
cxd2880_tnrdmd_lna_thrs_tbl_air
|
||
|
|
*tbl_air,
|
||
|
|
struct
|
||
|
|
cxd2880_tnrdmd_lna_thrs_tbl_cable
|
||
|
|
*tbl_cable);
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
struct
|
||
|
|
cxd2880_tnrdmd_lna_thrs_tbl_air
|
||
|
|
*tbl_air,
|
||
|
|
struct
|
||
|
|
cxd2880_tnrdmd_lna_thrs_tbl_cable
|
||
|
|
*tbl_cable);
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd
|
||
|
|
*tnr_dmd, u8 en, u8 value);
|
||
|
|
|
||
|
|
int cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd,
|
||
|
|
u8 en);
|
||
|
|
|
||
|
|
int slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd);
|
||
|
|
|
||
|
|
#endif
|