76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef __DBGTOP_H__
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#define __DBGTOP_H__
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#define MTK_DBGTOP_TEST 0
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#define DBGTOP_MAX_CMD_LEN 4
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#define MTK_DBGTOP_MODE (DBGTOP_BASE+0x0000)
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#define MTK_DBGTOP_DEBUG_CTL (DBGTOP_BASE+0x0030)
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#define MTK_DBGTOP_DEBUG_CTL2 (DBGTOP_BASE+0x0034)
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#define MTK_DBGTOP_LATCH_CTL (DBGTOP_BASE+0x0040)
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#define MTK_DBGTOP_LATCH_CTL2 (DBGTOP_BASE+LATCH_CTL2_OFFSET)
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#define MTK_DBGTOP_MFG_REG (DBGTOP_BASE+0x0060)
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/* TOPRGU debug register offset */
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#define MTK_RGU_DEBUG_CTL (DBGTOP_BASE+0x0040)
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#define MTK_RGU_DEBUG_CTL2 (DBGTOP_BASE+0x00A0)
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#define MTK_RGU_LATCH_CTL (DBGTOP_BASE+0x0044)
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#define MTK_RGU_LATCH_CTL2 (DBGTOP_BASE+0x0048)
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#if defined(CONFIG_MACH_MT6781)
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#define MTK_RGU_MFG_EN (DBGTOP_BASE+0x0068)
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#endif
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#define MTK_RGU_DVFSRC_PAUSE_PULSE (0x00008000)
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#define MTK_RGU_MODE_DDR_RESERVE (0x0080)
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/* DBGTOP_MODE */
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#define MTK_DBGTOP_MODE_KEY (0x22000000)
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#define MTK_DBGTOP_MODE_DDR_RESERVE (0x00000001)
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/* DBGTOP_DEBUG_CTL */
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#define MTK_DBGTOP_DEBUG_CTL_KEY (0x59000000)
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#define MTK_DBGTOP_DVFSRC_PAUSE_PULSE (0x00080000)
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#define MTK_DBGTOP_DVFSRC_SUCECESS_ACK (0x00800000)
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/* DBGTOP_DEBUG_CTL2 */
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#define MTK_DBGTOP_DEBUG_CTL2_KEY (0x55000000)
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#define MTK_DBGTOP_DVFSRC_EN (0x00000200)
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/* DBGTOP_LATCH_CTL */
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#define MTK_DBGTOP_LATCH_CTL_KEY (0x95000000)
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#define MTK_DBGTOP_DVFSRC_LATCH_EN (0x00002000)
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/* DBGTOP_LATCH_CTL2 */
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#define MTK_DBGTOP_LATCH_CTL2_KEY (0x95000000)
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#define MTK_DBGTOP_DFD_EN (0x00020000) /* (1<<17) */
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#define MTK_DBGTOP_DFD_THERM1_DIS (0x00040000) /* (1<<18) */
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#define MTK_DBGTOP_DFD_THERM2_DIS (0x00080000) /* (1<<19) */
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#define MTK_DBGTOP_DFD_TIMEOUT_SHIFT (0) /* bit(16:0) */
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#define MTK_DBGTOP_DFD_TIMEOUT_MASK \
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(0x1FFFF << MTK_DBGTOP_DFD_TIMEOUT_SHIFT)
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/* DBGTOP_MFG_REG */
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#define MTK_DBGTOP_MFG_REG_KEY (0x77000000)
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#define MTK_DBGTOP_MFG_PWR_ON (0x00000001)
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#define MTK_DBGTOP_MFG_PWR_EN (0x00000002)
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int mtk_dbgtop_dram_reserved(int enable);
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int mtk_dbgtop_cfg_dvfsrc(int enable);
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int mtk_dbgtop_pause_dvfsrc(int enable);
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int mtk_dbgtop_dfd_count_en(int value);
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int mtk_dbgtop_dfd_therm1_dis(int value);
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int mtk_dbgtop_dfd_therm2_dis(int value);
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int mtk_dbgtop_dfd_timeout(int value);
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int mtk_dbgtop_mfg_pwr_on(int value);
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int mtk_dbgtop_mfg_pwr_en(int value);
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void get_dfd_base(void __iomem *dfd_base, unsigned int latch_offset);
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#endif
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