351 lines
8 KiB
C
351 lines
8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2008 Openmoko, Inc.
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// Copyright 2008 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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// http://armlinux.simtec.co.uk/
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//
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// S3C64XX CPU PM support.
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/pm_domain.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/wakeup-mask.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <mach/gpio-samsung.h>
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#include "regs-gpio-memport.h"
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#include "regs-modem.h"
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#include "regs-sys.h"
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#include "regs-syscon-power.h"
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struct s3c64xx_pm_domain {
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char *const name;
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u32 ena;
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u32 pwr_stat;
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struct generic_pm_domain pd;
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};
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static int s3c64xx_pd_off(struct generic_pm_domain *domain)
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{
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struct s3c64xx_pm_domain *pd;
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u32 val;
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pd = container_of(domain, struct s3c64xx_pm_domain, pd);
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val = __raw_readl(S3C64XX_NORMAL_CFG);
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val &= ~(pd->ena);
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__raw_writel(val, S3C64XX_NORMAL_CFG);
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return 0;
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}
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static int s3c64xx_pd_on(struct generic_pm_domain *domain)
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{
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struct s3c64xx_pm_domain *pd;
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u32 val;
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long retry = 1000000L;
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pd = container_of(domain, struct s3c64xx_pm_domain, pd);
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val = __raw_readl(S3C64XX_NORMAL_CFG);
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val |= pd->ena;
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__raw_writel(val, S3C64XX_NORMAL_CFG);
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/* Not all domains provide power status readback */
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if (pd->pwr_stat) {
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do {
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cpu_relax();
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if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
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break;
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} while (retry--);
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if (!retry) {
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pr_err("Failed to start domain %s\n", pd->name);
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return -EBUSY;
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}
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}
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return 0;
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}
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static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
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.name = "IROM",
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.ena = S3C64XX_NORMALCFG_IROM_ON,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
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.name = "ETM",
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.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_s = {
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.name = "S",
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.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_S,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_f = {
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.name = "F",
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.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_F,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_p = {
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.name = "P",
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.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_P,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_i = {
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.name = "I",
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.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_I,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_g = {
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.name = "G",
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.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_v = {
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.name = "V",
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.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_V,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
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&s3c64xx_pm_irom,
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};
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static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
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&s3c64xx_pm_etm,
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&s3c64xx_pm_g,
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&s3c64xx_pm_v,
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&s3c64xx_pm_i,
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&s3c64xx_pm_p,
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&s3c64xx_pm_s,
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&s3c64xx_pm_f,
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};
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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void s3c_pm_debug_smdkled(u32 set, u32 clear)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < 4; i++) {
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if (clear & (1 << i))
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gpio_set_value(S3C64XX_GPN(12 + i), 0);
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if (set & (1 << i))
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gpio_set_value(S3C64XX_GPN(12 + i), 1);
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}
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local_irq_restore(flags);
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}
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#endif
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save core_save[] = {
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SAVE_ITEM(S3C64XX_MEM0DRVCON),
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SAVE_ITEM(S3C64XX_MEM1DRVCON),
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};
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static struct sleep_save misc_save[] = {
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SAVE_ITEM(S3C64XX_AHB_CON0),
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SAVE_ITEM(S3C64XX_AHB_CON1),
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SAVE_ITEM(S3C64XX_AHB_CON2),
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SAVE_ITEM(S3C64XX_SPCON),
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SAVE_ITEM(S3C64XX_MEM0CONSTOP),
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SAVE_ITEM(S3C64XX_MEM1CONSTOP),
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SAVE_ITEM(S3C64XX_MEM0CONSLP0),
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SAVE_ITEM(S3C64XX_MEM0CONSLP1),
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SAVE_ITEM(S3C64XX_MEM1CONSLP),
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SAVE_ITEM(S3C64XX_SDMA_SEL),
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SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
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SAVE_ITEM(S3C64XX_NORMAL_CFG),
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};
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void s3c_pm_configure_extint(void)
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{
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__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
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}
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void s3c_pm_restore_core(void)
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{
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__raw_writel(0, S3C64XX_EINT_MASK);
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s3c_pm_debug_smdkled(1 << 2, 0);
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s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
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s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
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}
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#endif
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/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
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* put the per-cpu code in here until any new cpu comes along and changes
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* this.
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*/
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static int s3c64xx_cpu_suspend(unsigned long arg)
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{
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unsigned long tmp;
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/* set our standby method to sleep */
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tmp = __raw_readl(S3C64XX_PWR_CFG);
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tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
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tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
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__raw_writel(tmp, S3C64XX_PWR_CFG);
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/* clear any old wakeup */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
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S3C64XX_WAKEUP_STAT);
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/* set the LED state to 0110 over sleep */
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s3c_pm_debug_smdkled(3 << 1, 0xf);
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/* issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case */
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tmp = 0;
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
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/* we should never get past here */
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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/* mapping of interrupts to parts of the wakeup mask */
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static const struct samsung_wakeup_mask wake_irqs[] = {
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{ .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
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{ .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
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{ .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
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{ .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
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{ .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
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{ .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
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};
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static void s3c64xx_pm_prepare(void)
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{
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samsung_sync_wakemask(S3C64XX_PWR_CFG,
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wake_irqs, ARRAY_SIZE(wake_irqs));
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/* store address of resume. */
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__raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
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/* ensure previous wakeup state is cleared before sleeping */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
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}
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int __init s3c64xx_pm_init(void)
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{
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int i;
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s3c_pm_init();
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for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
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pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
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&pm_domain_always_on_gov, false);
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for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
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pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
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#ifdef CONFIG_S3C_DEV_FB
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if (dev_get_platdata(&s3c_device_fb.dev))
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pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
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#endif
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return 0;
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}
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static __init int s3c64xx_pm_initcall(void)
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{
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if (!soc_is_s3c64xx())
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return 0;
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pm_cpu_prep = s3c64xx_pm_prepare;
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pm_cpu_sleep = s3c64xx_cpu_suspend;
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
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gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
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gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
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gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
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gpio_direction_output(S3C64XX_GPN(12), 0);
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gpio_direction_output(S3C64XX_GPN(13), 0);
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gpio_direction_output(S3C64XX_GPN(14), 0);
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|
|
gpio_direction_output(S3C64XX_GPN(15), 0);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
arch_initcall(s3c64xx_pm_initcall);
|