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kernel_samsung_a34x-permissive/arch/arm64/boot/dts/amlogic/meson-axg.dtsi

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Import A346BXXU1AWB9 kernel source Android 13
2024-04-28 06:49:01 -07:00
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
/ {
compatible = "amlogic,meson-axg";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 16 MiB reserved for Hardware ROM Firmware */
hwrom_reserved: hwrom@0 {
reg = <0x0 0x0 0x0 0x1000000>;
no-map;
};
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
tdmif_a: audio-controller@0 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_A";
clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
<&clkc_audio AUD_CLKID_MST_A_SCLK>,
<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
tdmif_b: audio-controller@1 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_B";
clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
<&clkc_audio AUD_CLKID_MST_B_SCLK>,
<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
tdmif_c: audio-controller@2 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_C";
clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
<&clkc_audio AUD_CLKID_MST_C_SCLK>,
<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
ao_alt_xtal: ao_alt_xtal-clk {
compatible = "fixed-clock";
clock-frequency = <32000000>;
clock-output-names = "ao_alt_xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb: apb@ffe00000 {
compatible = "simple-bus";
reg = <0x0 0xffe00000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
sd_emmc_b: sd@5000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x5000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_c: mmc@7000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
};
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};
tdmin_a: audio-controller@300 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x300 0x0 0x40>;
sound-name-prefix = "TDMIN_A";
clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_b: audio-controller@340 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x340 0x0 0x40>;
sound-name-prefix = "TDMIN_B";
clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_c: audio-controller@380 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x380 0x0 0x40>;
sound-name-prefix = "TDMIN_C";
clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_lb: audio-controller@3c0 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x3c0 0x0 0x40>;
sound-name-prefix = "TDMIN_LB";
clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
spdifout: audio-controller@480 {
compatible = "amlogic,axg-spdifout";
reg = <0x0 0x480 0x0 0x50>;
#sound-dai-cells = <0>;
sound-name-prefix = "SPDIFOUT";
clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
clock-names = "pclk", "mclk";
status = "disabled";
};
tdmout_a: audio-controller@500 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x500 0x0 0x40>;
sound-name-prefix = "TDMOUT_A";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmout_b: audio-controller@540 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x540 0x0 0x40>;
sound-name-prefix = "TDMOUT_B";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmout_c: audio-controller@580 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x580 0x0 0x40>;
sound-name-prefix = "TDMOUT_C";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
gpio_intc: interrupt-controller@f080 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x0 0xf080 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
pwm_ab: pwm@1b000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1b000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@1a000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1a000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
reset: reset-controller@1004 {
compatible = "amlogic,meson-axg-reset";
reg = <0x0 0x01004 0x0 0x9c>;
#reset-cells = <1>;
};
spicc0: spi@13000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x13000 0x0 0x3c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@15000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x15000 0x0 0x3c>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@1f000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1f000 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@1e000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1e000 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@1d000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1d000 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@1c000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1c000 0x0 0x20>;
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000
0x0 0xff634540 0x0 0x8>;
interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
status = "disabled";
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
clkc: clock-controller {
compatible = "amlogic,axg-clkc";
#clock-cells = <1>;
};
};
};
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
periphs: periphs@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x18 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@480 {
reg = <0x0 0x00480 0x0 0x40>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x3c>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_clk",
"emmc_cmd",
"emmc_ds";
function = "emmc";
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "BOOT_8";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "BOOT_8";
bias-pull-down;
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
};
};
eth_rmii_x_pins: eth-x-rmii {
mux {
groups = "eth_mdio_x",
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x";
function = "eth";
};
};
eth_rmii_y_pins: eth-y-rmii {
mux {
groups = "eth_mdio_y",
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y";
function = "eth";
};
};
eth_rgmii_x_pins: eth-x-rgmii {
mux {
groups = "eth_mdio_x",
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
};
};
eth_rgmii_y_pins: eth-y-rgmii {
mux {
groups = "eth_mdio_y",
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
};
};
pdm_dclk_a14_pins: pdm_dclk_a14 {
mux {
groups = "pdm_dclk_a14";
function = "pdm";
};
};
pdm_dclk_a19_pins: pdm_dclk_a19 {
mux {
groups = "pdm_dclk_a19";
function = "pdm";
};
};
pdm_din0_pins: pdm_din0 {
mux {
groups = "pdm_din0";
function = "pdm";
};
};
pdm_din1_pins: pdm_din1 {
mux {
groups = "pdm_din1";
function = "pdm";
};
};
pdm_din2_pins: pdm_din2 {
mux {
groups = "pdm_din2";
function = "pdm";
};
};
pdm_din3_pins: pdm_din3 {
mux {
groups = "pdm_din3";
function = "pdm";
};
};
pwm_a_a_pins: pwm_a_a {
mux {
groups = "pwm_a_a";
function = "pwm_a";
};
};
pwm_a_x18_pins: pwm_a_x18 {
mux {
groups = "pwm_a_x18";
function = "pwm_a";
};
};
pwm_a_x20_pins: pwm_a_x20 {
mux {
groups = "pwm_a_x20";
function = "pwm_a";
};
};
pwm_a_z_pins: pwm_a_z {
mux {
groups = "pwm_a_z";
function = "pwm_a";
};
};
pwm_b_a_pins: pwm_b_a {
mux {
groups = "pwm_b_a";
function = "pwm_b";
};
};
pwm_b_x_pins: pwm_b_x {
mux {
groups = "pwm_b_x";
function = "pwm_b";
};
};
pwm_b_z_pins: pwm_b_z {
mux {
groups = "pwm_b_z";
function = "pwm_b";
};
};
pwm_c_a_pins: pwm_c_a {
mux {
groups = "pwm_c_a";
function = "pwm_c";
};
};
pwm_c_x10_pins: pwm_c_x10 {
mux {
groups = "pwm_c_x10";
function = "pwm_c";
};
};
pwm_c_x17_pins: pwm_c_x17 {
mux {
groups = "pwm_c_x17";
function = "pwm_c";
};
};
pwm_d_x11_pins: pwm_d_x11 {
mux {
groups = "pwm_d_x11";
function = "pwm_d";
};
};
pwm_d_x16_pins: pwm_d_x16 {
mux {
groups = "pwm_d_x16";
function = "pwm_d";
};
};
spdif_in_z_pins: spdif_in_z {
mux {
groups = "spdif_in_z";
function = "spdif_in";
};
};
spdif_in_a1_pins: spdif_in_a1 {
mux {
groups = "spdif_in_a1";
function = "spdif_in";
};
};
spdif_in_a7_pins: spdif_in_a7 {
mux {
groups = "spdif_in_a7";
function = "spdif_in";
};
};
spdif_in_a19_pins: spdif_in_a19 {
mux {
groups = "spdif_in_a19";
function = "spdif_in";
};
};
spdif_in_a20_pins: spdif_in_a20 {
mux {
groups = "spdif_in_a20";
function = "spdif_in";
};
};
spdif_out_z_pins: spdif_out_z {
mux {
groups = "spdif_out_z";
function = "spdif_out";
};
};
spdif_out_a1_pins: spdif_out_a1 {
mux {
groups = "spdif_out_a1";
function = "spdif_out";
};
};
spdif_out_a11_pins: spdif_out_a11 {
mux {
groups = "spdif_out_a11";
function = "spdif_out";
};
};
spdif_out_a19_pins: spdif_out_a19 {
mux {
groups = "spdif_out_a19";
function = "spdif_out";
};
};
spdif_out_a20_pins: spdif_out_a20 {
mux {
groups = "spdif_out_a20";
function = "spdif_out";
};
};
spi0_pins: spi0 {
mux {
groups = "spi0_miso",
"spi0_mosi",
"spi0_clk";
function = "spi0";
};
};
spi0_ss0_pins: spi0_ss0 {
mux {
groups = "spi0_ss0";
function = "spi0";
};
};
spi0_ss1_pins: spi0_ss1 {
mux {
groups = "spi0_ss1";
function = "spi0";
};
};
spi0_ss2_pins: spi0_ss2 {
mux {
groups = "spi0_ss2";
function = "spi0";
};
};
spi1_a_pins: spi1_a {
mux {
groups = "spi1_miso_a",
"spi1_mosi_a",
"spi1_clk_a";
function = "spi1";
};
};
spi1_ss0_a_pins: spi1_ss0_a {
mux {
groups = "spi1_ss0_a";
function = "spi1";
};
};
spi1_ss1_pins: spi1_ss1 {
mux {
groups = "spi1_ss1";
function = "spi1";
};
};
spi1_x_pins: spi1_x {
mux {
groups = "spi1_miso_x",
"spi1_mosi_x",
"spi1_clk_x";
function = "spi1";
};
};
spi1_ss0_x_pins: spi1_ss0_x {
mux {
groups = "spi1_ss0_x";
function = "spi1";
};
};
i2c0_pins: i2c0 {
mux {
groups = "i2c0_sck",
"i2c0_sda";
function = "i2c0";
};
};
i2c1_z_pins: i2c1_z {
mux {
groups = "i2c1_sck_z",
"i2c1_sda_z";
function = "i2c1";
};
};
i2c1_x_pins: i2c1_x {
mux {
groups = "i2c1_sck_x",
"i2c1_sda_x";
function = "i2c1";
};
};
i2c2_x_pins: i2c2_x {
mux {
groups = "i2c2_sck_x",
"i2c2_sda_x";
function = "i2c2";
};
};
i2c2_a_pins: i2c2_a {
mux {
groups = "i2c2_sck_a",
"i2c2_sda_a";
function = "i2c2";
};
};
i2c3_a6_pins: i2c3_a6 {
mux {
groups = "i2c3_sda_a6",
"i2c3_sck_a7";
function = "i2c3";
};
};
i2c3_a12_pins: i2c3_a12 {
mux {
groups = "i2c3_sda_a12",
"i2c3_sck_a13";
function = "i2c3";
};
};
i2c3_a19_pins: i2c3_a19 {
mux {
groups = "i2c3_sda_a19",
"i2c3_sck_a20";
function = "i2c3";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_a_cts_rts_pins: uart_a_cts_rts {
mux {
groups = "uart_cts_a",
"uart_rts_a";
function = "uart_a";
};
};
uart_b_x_pins: uart_b_x {
mux {
groups = "uart_tx_b_x",
"uart_rx_b_x";
function = "uart_b";
};
};
uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
mux {
groups = "uart_cts_b_x",
"uart_rts_b_x";
function = "uart_b";
};
};
uart_b_z_pins: uart_b_z {
mux {
groups = "uart_tx_b_z",
"uart_rx_b_z";
function = "uart_b";
};
};
uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
mux {
groups = "uart_cts_b_z",
"uart_rts_b_z";
function = "uart_b";
};
};
uart_ao_b_z_pins: uart_ao_b_z {
mux {
groups = "uart_ao_tx_b_z",
"uart_ao_rx_b_z";
function = "uart_ao_b_z";
};
};
uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
mux {
groups = "uart_ao_cts_b_z",
"uart_ao_rts_b_z";
function = "uart_ao_b_z";
};
};
mclk_b_pins: mclk_b {
mux {
groups = "mclk_b";
function = "mclk_b";
};
};
mclk_c_pins: mclk_c {
mux {
groups = "mclk_c";
function = "mclk_c";
};
};
tdma_sclk_pins: tdma_sclk {
mux {
groups = "tdma_sclk";
function = "tdma";
};
};
tdma_sclk_slv_pins: tdma_sclk_slv {
mux {
groups = "tdma_sclk_slv";
function = "tdma";
};
};
tdma_fs_pins: tdma_fs {
mux {
groups = "tdma_fs";
function = "tdma";
};
};
tdma_fs_slv_pins: tdma_fs_slv {
mux {
groups = "tdma_fs_slv";
function = "tdma";
};
};
tdma_din0_pins: tdma_din0 {
mux {
groups = "tdma_din0";
function = "tdma";
};
};
tdma_dout0_x14_pins: tdma_dout0_x14 {
mux {
groups = "tdma_dout0_x14";
function = "tdma";
};
};
tdma_dout0_x15_pins: tdma_dout0_x15 {
mux {
groups = "tdma_dout0_x15";
function = "tdma";
};
};
tdma_dout1_pins: tdma_dout1 {
mux {
groups = "tdma_dout1";
function = "tdma";
};
};
tdma_din1_pins: tdma_din1 {
mux {
groups = "tdma_din1";
function = "tdma";
};
};
tdmb_sclk_pins: tdmb_sclk {
mux {
groups = "tdmb_sclk";
function = "tdmb";
};
};
tdmb_sclk_slv_pins: tdmb_sclk_slv {
mux {
groups = "tdmb_sclk_slv";
function = "tdmb";
};
};
tdmb_fs_pins: tdmb_fs {
mux {
groups = "tdmb_fs";
function = "tdmb";
};
};
tdmb_fs_slv_pins: tdmb_fs_slv {
mux {
groups = "tdmb_fs_slv";
function = "tdmb";
};
};
tdmb_din0_pins: tdmb_din0 {
mux {
groups = "tdmb_din0";
function = "tdmb";
};
};
tdmb_dout0_pins: tdmb_dout0 {
mux {
groups = "tdmb_dout0";
function = "tdmb";
};
};
tdmb_din1_pins: tdmb_din1 {
mux {
groups = "tdmb_din1";
function = "tdmb";
};
};
tdmb_dout1_pins: tdmb_dout1 {
mux {
groups = "tdmb_dout1";
function = "tdmb";
};
};
tdmb_din2_pins: tdmb_din2 {
mux {
groups = "tdmb_din2";
function = "tdmb";
};
};
tdmb_dout2_pins: tdmb_dout2 {
mux {
groups = "tdmb_dout2";
function = "tdmb";
};
};
tdmb_din3_pins: tdmb_din3 {
mux {
groups = "tdmb_din3";
function = "tdmb";
};
};
tdmb_dout3_pins: tdmb_dout3 {
mux {
groups = "tdmb_dout3";
function = "tdmb";
};
};
tdmc_sclk_pins: tdmc_sclk {
mux {
groups = "tdmc_sclk";
function = "tdmc";
};
};
tdmc_sclk_slv_pins: tdmc_sclk_slv {
mux {
groups = "tdmc_sclk_slv";
function = "tdmc";
};
};
tdmc_fs_pins: tdmc_fs {
mux {
groups = "tdmc_fs";
function = "tdmc";
};
};
tdmc_fs_slv_pins: tdmc_fs_slv {
mux {
groups = "tdmc_fs_slv";
function = "tdmc";
};
};
tdmc_din0_pins: tdmc_din0 {
mux {
groups = "tdmc_din0";
function = "tdmc";
};
};
tdmc_dout0_pins: tdmc_dout0 {
mux {
groups = "tdmc_dout0";
function = "tdmc";
};
};
tdmc_din1_pins: tdmc_din1 {
mux {
groups = "tdmc_din1";
function = "tdmc";
};
};
tdmc_dout1_pins: tdmc_dout1 {
mux {
groups = "tdmc_dout1";
function = "tdmc";
};
};
tdmc_din2_pins: tdmc_din2 {
mux {
groups = "tdmc_din2";
function = "tdmc";
};
};
tdmc_dout2_pins: tdmc_dout2 {
mux {
groups = "tdmc_dout2";
function = "tdmc";
};
};
tdmc_din3_pins: tdmc_din3 {
mux {
groups = "tdmc_din3";
function = "tdmc";
};
};
tdmc_dout3_pins: tdmc_dout3 {
mux {
groups = "tdmc_dout3";
function = "tdmc";
};
};
};
};
sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xfffc0000 0x20000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13400 0x400>;
};
};
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-axg-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
};
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-axg-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 15>;
};
i2c_ao_sck_4_pins: i2c_ao_sck_4 {
mux {
groups = "i2c_ao_sck_4";
function = "i2c_ao";
};
};
i2c_ao_sck_8_pins: i2c_ao_sck_8 {
mux {
groups = "i2c_ao_sck_8";
function = "i2c_ao";
};
};
i2c_ao_sck_10_pins: i2c_ao_sck_10 {
mux {
groups = "i2c_ao_sck_10";
function = "i2c_ao";
};
};
i2c_ao_sda_5_pins: i2c_ao_sda_5 {
mux {
groups = "i2c_ao_sda_5";
function = "i2c_ao";
};
};
i2c_ao_sda_9_pins: i2c_ao_sda_9 {
mux {
groups = "i2c_ao_sda_9";
function = "i2c_ao";
};
};
i2c_ao_sda_11_pins: i2c_ao_sda_11 {
mux {
groups = "i2c_ao_sda_11";
function = "i2c_ao";
};
};
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_ao_tx_a",
"uart_ao_rx_a";
function = "uart_ao_a";
};
};
uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
mux {
groups = "uart_ao_cts_a",
"uart_ao_rts_a";
function = "uart_ao_a";
};
};
uart_ao_b_pins: uart_ao_b {
mux {
groups = "uart_ao_tx_b",
"uart_ao_rx_b";
function = "uart_ao_b";
};
};
uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
mux {
groups = "uart_ao_cts_b",
"uart_ao_rts_b";
function = "uart_ao_b";
};
};
};
sec_AO: ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
amlogic,has-chip-id;
};
pwm_AO_ab: pwm@7000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x07000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_AO_cd: pwm@2000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x02000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
i2c_AO: i2c@5000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x05000 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_AO_B: serial@4000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
ir: ir@8000 {
compatible = "amlogic,meson-gxbb-ir";
reg = <0x0 0x8000 0x0 0x20>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
saradc: adc@9000 {
compatible = "amlogic,meson-axg-saradc",
"amlogic,meson-saradc";
reg = <0x0 0x9000 0x0 0x38>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>,
<&clkc_AO CLKID_AO_SAR_ADC>,
<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
clock-names = "clkin", "core", "adc_clk", "adc_sel";
status = "disabled";
};
};
};
};
Reference in a new issue Copy permalink