223 lines
7.7 KiB
C
223 lines
7.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_FHREG_H__
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#define __MT_FHREG_H__
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#include <linux/bitops.h>
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/* #include <mach/mt_reg_base.h> */
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/* **************************************************** */
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/* IP base address */
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/* **************************************************** */
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#ifdef CONFIG_ARM64
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#define REG_ADDR(x) ((unsigned long)g_fhctl_base + (x))
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#define REG_MCU_FHCTL_ADDR(x) ((unsigned long)g_mcu_fhctl_base + (x))
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#define REG_APMIX_ADDR(x) ((unsigned long)g_apmixed_base + (x))
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#define REG_MCUMIX_ADDR(x) ((unsigned long)g_mcumixed_base + (x))
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#define REG_DDRPHY_ADDR(x) ((unsigned long)g_ddrphy_base + (x))
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#else
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#define REG_ADDR(x) ((unsigned int)g_fhctl_base + (x))
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#define REG_MCU_FHCTL_ADDR(x) ((unsigned int)g_mcu_fhctl_base + (x))
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#define REG_APMIX_ADDR(x) ((unsigned int)g_apmixed_base + (x))
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#define REG_MCUMIX_ADDR(x) ((unsigned int)g_mcumixed_base + (x))
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#define REG_DDRPHY_ADDR(x) ((unsigned int)g_ddrphy_base + (x))
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#endif
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/* **************************************************** */
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/* FHCTL register */
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/* **************************************************** */
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#define REG_FHCTL_HP_EN REG_ADDR(0x0000)
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#define REG_FHCTL_CLK_CON REG_ADDR(0x0004)
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#define REG_FHCTL_RST_CON REG_ADDR(0x0008)
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#define REG_FHCTL_SLOPE0 REG_ADDR(0x000C)
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#define REG_FHCTL_SLOPE1 REG_ADDR(0x0010)
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#define REG_FHCTL_DSSC_CFG REG_ADDR(0x0014)
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#define REG_FHCTL_DSSC0_CON REG_ADDR(0x0018)
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#define REG_FHCTL_DSSC1_CON REG_ADDR(0x001C)
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#define REG_FHCTL_DSSC2_CON REG_ADDR(0x0020)
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#define REG_FHCTL_DSSC3_CON REG_ADDR(0x0024)
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#define REG_FHCTL_DSSC4_CON REG_ADDR(0x0028)
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#define REG_FHCTL_DSSC5_CON REG_ADDR(0x002C)
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#define REG_FHCTL_DSSC6_CON REG_ADDR(0x0030)
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#define REG_FHCTL_DSSC7_CON REG_ADDR(0x0034)
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#define REG_FHCTL0_CFG REG_ADDR(0x0038)
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#define REG_FHCTL0_UPDNLMT REG_ADDR(0x003C)
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#define REG_FHCTL0_DDS REG_ADDR(0x0040)
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#define REG_FHCTL0_DVFS REG_ADDR(0x0044)
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#define REG_FHCTL0_MON REG_ADDR(0x0048)
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#define REG_FHCTL1_CFG REG_ADDR(0x004C)
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#define REG_FHCTL1_UPDNLMT REG_ADDR(0x0050)
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#define REG_FHCTL1_DDS REG_ADDR(0x0054)
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#define REG_FHCTL1_DVFS REG_ADDR(0x0058)
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#define REG_FHCTL1_MON REG_ADDR(0x005C)
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#define REG_FHCTL2_CFG REG_ADDR(0x0060)
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#define REG_FHCTL2_UPDNLMT REG_ADDR(0x0064)
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#define REG_FHCTL2_DDS REG_ADDR(0x0068)
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#define REG_FHCTL2_DVFS REG_ADDR(0x006C)
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#define REG_FHCTL2_MON REG_ADDR(0x0070)
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#define REG_FHCTL3_CFG REG_ADDR(0x0074)
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#define REG_FHCTL3_UPDNLMT REG_ADDR(0x0078)
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#define REG_FHCTL3_DDS REG_ADDR(0x007C)
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#define REG_FHCTL3_DVFS REG_ADDR(0x0080)
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#define REG_FHCTL3_MON REG_ADDR(0x0084)
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#define REG_FHCTL4_CFG REG_ADDR(0x0088)
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#define REG_FHCTL4_UPDNLMT REG_ADDR(0x008C)
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#define REG_FHCTL4_DDS REG_ADDR(0x0090)
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#define REG_FHCTL4_DVFS REG_ADDR(0x0094)
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#define REG_FHCTL4_MON REG_ADDR(0x0098)
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#define REG_FHCTL5_CFG REG_ADDR(0x009C)
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#define REG_FHCTL5_UPDNLMT REG_ADDR(0x00A0)
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#define REG_FHCTL5_DDS REG_ADDR(0x00A4)
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#define REG_FHCTL5_DVFS REG_ADDR(0x00A8)
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#define REG_FHCTL5_MON REG_ADDR(0x00AC)
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/* **************************************************** */
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/* APMIXED CON0/CON1 Register */
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/* **************************************************** */
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#define REG_PLL_NOT_SUPPORT 0xdeadbeef
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/*CON0, PLL enable status */
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#define REG_ARMPLL_CON0 REG_APMIX_ADDR(0x0200)
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#define REG_ARMPLL2_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_ARMPLL3_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_CCIPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_GPUPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_MPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_MEMPLL_CON0 REG_PLL_NOT_SUPPORT /* It's in DDRPHY */
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#define REG_MAINPLL_CON0 REG_APMIX_ADDR(0x0220)
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#define REG_MFGPLL_CON0 REG_APMIX_ADDR(0x0240)
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#define REG_MSDCPLL_CON0 REG_APMIX_ADDR(0x0250)
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#define REG_MMPLL_CON0 REG_APMIX_ADDR(0x0270)
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#define REG_VDECPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_TVDPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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/*CON1, DDS value */
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#define REG_ARMPLL_CON1 REG_APMIX_ADDR(0x0204)
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#define REG_ARMPLL2_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_ARMPLL3_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_CCIPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_GPUPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_MPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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/* MEMPLL's dds value is in 0x1001E624[31:11] */
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#define REG_MEMPLL_CON1 REG_DDRPHY_ADDR(0x0624)
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#define REG_MAINPLL_CON1 REG_APMIX_ADDR(0x0224)
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#define REG_MFGPLL_CON1 REG_APMIX_ADDR(0x0244)
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#define REG_MSDCPLL_CON1 REG_APMIX_ADDR(0x0254)
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#define REG_MMPLL_CON1 REG_APMIX_ADDR(0x0274)
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#define REG_VDECPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_TVDPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in MT6739 */
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#define REG_FH_PLL0_CON0 REG_ARMPLL_CON0
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#define REG_FH_PLL1_CON0 REG_MAINPLL_CON0
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#define REG_FH_PLL2_CON0 REG_MSDCPLL_CON0
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#define REG_FH_PLL3_CON0 REG_MFGPLL_CON0
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#define REG_FH_PLL4_CON0 REG_MEMPLL_CON0
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#define REG_FH_PLL5_CON0 REG_MMPLL_CON0
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#define REG_FH_PLL0_CON1 REG_ARMPLL_CON1
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#define REG_FH_PLL1_CON1 REG_MAINPLL_CON1
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#define REG_FH_PLL2_CON1 REG_MSDCPLL_CON1
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#define REG_FH_PLL3_CON1 REG_MFGPLL_CON1
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#define REG_FH_PLL4_CON1 REG_MEMPLL_CON1
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#define REG_FH_PLL5_CON1 REG_MMPLL_CON1
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/***************************************************** */
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/* **************************************************** */
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/* FHCTL Register mask */
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/* **************************************************** */
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#define MASK_FRDDSX_DYS (0xFU<<20)
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#define MASK_FRDDSX_DTS (0xFU<<16)
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#define FH_FHCTLX_MON_SEL (0x3U<<5)
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#define FH_FHCTLX_PAUSE (0x1U<<4)
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#define FH_DYSSCX_EN (0x1U<<3)
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#define FH_SFSTRX_EN (0x1U<<2)
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#define FH_FRDDSX_EN (0x1U<<1)
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#define FH_FHCTLX_EN (0x1U<<0)
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#define FH_FRDDSX_DNLMT (0xFFU<<16)
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#define FH_FRDDSX_UPLMT (0xFFU)
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#define FH_FHCTLX_PLL_TGL_ORG (0x1U<<31)
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#define FH_FHCTLX_PLL_ORG (0x3FFFFU) /* Note that bit21 is invalid */
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#define FH_MON_FHCTLX_PAUSE (0x1U<<31)
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#define FH_MON_FHCTLX_PRD (0x1U<<30)
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#define FH_MON_SFSTRX_PRD (0x1U<<29)
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#define FH_MON_FRDDSX_PRD (0x1U<<28)
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#define FH_FHCTLX_STATE (0xFU<<24)
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#define FH_FHCTLX_PLL_DDS (0x3FFFFU)
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/* **************************************************** */
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/* Macro */
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/* **************************************************** */
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static inline unsigned int uffs(unsigned int x)
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{
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unsigned int r = 1;
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if (!x)
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return 0;
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if (!(x & 0xffff)) {
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x >>= 16;
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r += 16;
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}
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if (!(x & 0xff)) {
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x >>= 8;
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r += 8;
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}
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if (!(x & 0xf)) {
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x >>= 4;
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r += 4;
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}
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if (!(x & 3)) {
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x >>= 2;
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r += 2;
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}
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if (!(x & 1)) {
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x >>= 1;
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r += 1;
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}
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return r;
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}
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#define fh_read8(reg) readb(reg)
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#define fh_read16(reg) readw(reg)
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#define fh_read32(reg) readl((void __iomem *)reg)
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#define fh_write8(reg, val) mt_reg_sync_writeb((val), (reg))
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#define fh_write16(reg, val) mt_reg_sync_writew((val), (reg))
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#define fh_write32(reg, val) mt_reg_sync_writel((val), (reg))
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#define fh_set_field(reg, field, val) \
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do { \
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unsigned int tv = fh_read32(reg); \
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tv &= ~(field); \
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tv |= ((val) << (uffs((unsigned int)field) - 1)); \
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fh_write32(reg, tv); \
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} while (0)
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#define fh_get_field(reg, field, val) \
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do { \
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unsigned int tv = fh_read32(reg); \
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val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
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} while (0)
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#endif /* #ifndef __MT_FHREG_H__ */
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