67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRAMC_H__
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#define __DRAMC_H__
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/* Feature options */
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#ifdef CONFIG_MTK_EMI_LEGACY
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#define EMI_READY
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#endif
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/* #define RUNTIME_SHMOO */
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#if defined(CONFIG_MTK_ENG_BUILD)
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#define DRAMC_MEMTEST_DEBUG_SUPPORT
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#endif
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/* Registers define */
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#define PDEF_DRAMC0_CHA_REG_0E4 IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x00e4))
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#define PDEF_SPM_AP_SEMAPHORE IOMEM((SLEEP_BASE_ADDR + 0x428))
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/* Define */
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#define PATTERN1 0x5A5A5A5A
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#define PATTERN2 0xA5A5A5A5
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/* DRAMC API config */
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extern void __iomem *mt_emi_base_get(void);
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unsigned int mt_dramc_chn_get(unsigned int emi_cona);
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unsigned int mt_dramc_chp_get(unsigned int emi_cona);
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phys_addr_t mt_dramc_rankbase_get(unsigned int rank);
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unsigned int mt_dramc_ta_support_ranks(void);
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void *mt_dramc_chn_base_get(int channel);
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void *mt_dramc_nao_chn_base_get(int channel);
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void *mt_ddrphy_chn_base_get(int channel);
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void *mt_ddrphy_nao_chn_base_get(int channel);
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unsigned int get_dram_data_rate(void);
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int dram_steps_freq(unsigned int step);
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unsigned int get_shuffle_status(void);
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int get_ddr_type(void);
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unsigned char get_ddr_mr(unsigned int index);
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int get_emi_ch_num(void);
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unsigned int lpDram_Register_Read(unsigned int Reg_base, unsigned int Offset);
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int enter_pasr_dpd_config(unsigned char segment_rank0,
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unsigned char segment_rank1);
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int exit_pasr_dpd_config(void);
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enum DDRTYPE {
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TYPE_LPDDR3 = 1,
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TYPE_LPDDR4,
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TYPE_LPDDR4X
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};
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enum {
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DRAMC_NAO_CHA = 0,
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DRAMC_NAO_CHB,
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DRAMC_AO_CHA,
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DRAMC_AO_CHB,
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PHY_NAO_CHA,
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PHY_NAO_CHB,
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PHY_AO_CHA,
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PHY_AO_CHB
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}; /* RegBase */
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#endif /*__WDT_HW_H__*/
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